参数资料
型号: AT90LS2343-1SI
厂商: Atmel
文件页数: 62/63页
文件大小: 0K
描述: IC MCU 2K FLASH 1MHZ IND 8-SOIC
标准包装: 95
系列: AVR® 90LS
核心处理器: AVR
芯体尺寸: 8-位
速度: 1MHz
连通性: SPI
外围设备: 欠压检测/复位,POR,WDT
输入/输出数: 5
程序存储器容量: 2KB(1K x 16)
程序存储器类型: 闪存
EEPROM 大小: 128 x 8
RAM 容量: 128 x 8
电压 - 电源 (Vcc/Vdd): 2.7 V ~ 6 V
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 8-SOIC(0.209",5.30mm 宽)
包装: 管件
8
AT90S/LS2323/2343
1004D–09/01
The AVR has Harvard architecture – with separate memories and buses for program
and data. The program memory is accessed with a two-stage pipeline. While one
instruction is being executed, the next instruction is pre-fetched from the program mem-
ory. This concept enables instructions to be executed in every clock cycle. The program
memory is in-system downloadable Flash memory.
With the relative jump and call instructions, the whole 1K address space is directly
accessed. Most AVR instructions have a single 16-bit word format. Every program
memory address contains a 16- or 32-bit instruction.
During interrupts and subroutine calls, the return address Program Counter (PC) is
stored on the stack. The stack is effectively allocated in the general data SRAM and
consequently, the stack size is only limited by the total SRAM size and the usage of the
SRAM. All user programs must initialize the SP in the reset routine (before subroutines
or interrupts are executed). The 8-bit stack pointer (SP) is read/write-accessible in the
I/O space.
The 128 bytes data SRAM + register file and I/O registers can be easily accessed
through the five different addressing modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
Figure 6. Memory Maps
A flexible interrupt module has its control registers in the I/O space with an additional
global interrupt enable bit in the status register. All the different interrupts have a sepa-
rate interrupt vector in the interrupt vector table at the beginning of the program
memory. The different interrupts have priority in accordance with their interrupt vector
position. The lower the interrupt vector address, the higher the priority.
EEPROM
(128 x 8)
$000
$07F
EEPROM Data Memory
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