参数资料
型号: AT90LS2343-1SI
厂商: Atmel
文件页数: 48/63页
文件大小: 0K
描述: IC MCU 2K FLASH 1MHZ IND 8-SOIC
标准包装: 95
系列: AVR® 90LS
核心处理器: AVR
芯体尺寸: 8-位
速度: 1MHz
连通性: SPI
外围设备: 欠压检测/复位,POR,WDT
输入/输出数: 5
程序存储器容量: 2KB(1K x 16)
程序存储器类型: 闪存
EEPROM 大小: 128 x 8
RAM 容量: 128 x 8
电压 - 电源 (Vcc/Vdd): 2.7 V ~ 6 V
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 8-SOIC(0.209",5.30mm 宽)
包装: 管件
2002 Microchip Technology Inc.
Preliminary
DS41139B-page 51
PIC16C433
9.0
SPECIAL FEATURES OF THE
CPU
What sets a microcontroller apart from other proces-
sors are special circuits to deal with the needs of real-
time applications. The PIC16C433 device has a host of
such features intended to maximize system reliability,
minimize cost through elimination of external compo-
nents, provide power saving operating modes and offer
code protection. These are:
Oscillator Selection
RESET
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
Interrupts
Watchdog Timer (WDT)
SLEEP
Code Protection
ID Locations
In-Circuit Serial Programming
The PIC16C433 has a Watchdog Timer, which can be
shut-off only through configuration bits. It runs off its
own RC oscillator for added reliability. There are two
timers that offer necessary delays on power-up. One is
the Oscillator Start-up Timer (OST), intended to keep
the chip in RESET until the crystal oscillator is stable.
The other is the Power-up Timer (PWRT), which pro-
vides a fixed delay of 72 ms (nominal) on power-up
only, designed to keep the part in RESET while the
power supply stabilizes. With these two timers on-chip,
most applications need no external RESET circuitry.
SLEEP mode is designed to offer a very low current
Power-down mode. The user can wake-up from
SLEEP through external RESET, Watchdog Timer
wake-up, or through an interrupt. Several oscillator
options are also made available to allow the part to fit
the application. The INTRC/EXTRC oscillator option
saves system cost, while the LP crystal option saves
power. A set of configuration bits is used to select vari-
ous options.
9.1
Configuration Bits
The configuration bits can be programmed (read as '0'),
or left unprogrammed (read as '1'), to select various
device configurations. These bits are mapped in pro-
gram memory location 2007h.
The user will note that address 2007h is beyond the
user program memory space. In fact, it belongs to the
special test/configuration memory space (2000h-
3FFFh),
which
can
be
accessed
only
during
programming.
REGISTER 9-1:
CONFIG — CONFIGURATION WORD (ADDRESS: 2007H)
CP
BORV1
BORV0
CP
BODEN
MCLRE
PWRTE
WDTE
FOSC2
FOSC1
FOSC0
bit13
bit0
bit 13-8, 6-5:
CP<1:0>: Code Protection bit pairs(1)
11 = Code protection off
10 = Locations 400h through 7FEh code protected
01 = Locations 200h through 7FEh code protected
00 = All memory is code protected
bit 7:
MCLRE: Master Clear Reset Enable bit
1 = Master Clear enabled
0 = Master Clear disabled
bit 4:
PWRTE: Power-up Timer Enable bit
1 = PWRT disabled
0 = PWRT enabled
bit 3:
WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 2-0:
FOSC<2:0>: Oscillator Selection bits
111 = EXTRC, clockout on OSC2
110 = EXTRC, OSC2 is I/O
101 = INTRC, clockout on OSC2
100 = INTRC, OSC2 is I/O
011 = Invalid selection
010 = HS oscillator
001 = XT oscillator
000 = LP oscillator
Note:
All of the CP<1:0> pairs have to be given the same value to enable the code protection scheme listed.
Legend
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
1 = bit is set
0 = bit is cleared
x = bit is unknown
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