参数资料
型号: ATAM893T-TKQ
厂商: Atmel
文件页数: 65/98页
文件大小: 0K
描述: IC MON TIRE-PRESS ATARX9X SER
标准包装: 4,000
系列: MARC4
核心处理器: MARC4
芯体尺寸: 4-位
速度: 4MHz
连通性: SSI(2 线,3 线)
外围设备: 欠压检测/复位,POR,PWM,WDT
输入/输出数: 16
程序存储器容量: 4KB(4K x 8)
程序存储器类型: EEPROM
EEPROM 大小: 64 x 16
RAM 容量: 256 x 4
电压 - 电源 (Vcc/Vdd): 1.8 V ~ 6.5 V
振荡器型: 内部
工作温度: -40°C ~ 125°C
封装/外壳: 20-SOIC(0.209",5.30mm 宽)
包装: 带卷 (TR)
68
4680C–4BMCU–01/05
ATAM893-D
5.3.4.9
Modulation and Demodulation
If the shift register is used together with Timer 2 or Timer 3 for modulation or demodulation pur-
poses, the 8-bit synchronous mode must be used. In this case, the unused Port 4 pins can be
used as conventional bi-directional ports.
The modulation and demodulation stages, if enabled, operate as soon as the SSI is activated
(SIR = 0) and cease when deactivated (SIR = 1).
Due to the byte-orientated data control, the SSI (when running normally) generates serial bit
streams which are submultiples of 8 bits. An SSI output masking (OMSK) function permits, how-
ever, the generation of bit streams of any length. The OMSK signal is derived indirectly from the
4-bit prescaler of the Timer 2 and masks out a programmable number of unrequited trailing data
bits during the shifting out of the final data word in the bit stream. The number of non-masked
data bits is defined by the value pre-programmed in the prescaler compare register. To use out-
put masking, the modulator stop mode bit (MSM) must be set to’0’ before programming the final
data word into the SSI transmit buffer. This in turn, enables shift clocks to the prescaler when
this final word is shifted out. On reaching the compare value, the prescaler triggers the OMSK
signal and all following data bits are blanked.
5.3.4.10
Internal 2-wire Multi-chip Link
Two additional on-chip pads (MCL_SC and MCL_SD) for the SC and the SD line can be used as
chip-to-chip link for multi-chip applications. These pads can be activated by setting the MCL bit
in the SISC register. They are also used as interface to the internal data EEPROM
Figure 5-46. Multi-chip Link
Figure 5-47. SSI Output Masking Function
SCL
SDA
MCL_SC
MCL_SD
U505M
Microcontroller
V DD
BP40/SC
BP10
BP43/SD
BP13
Multi-chip link
V SS
8-bit shift register
MSB
LSB
Shift_CL
SO
Control
SI
Timer 2
Output
SSI-control
SO
Compare 2/1
4-bit counter 2/1
CL2/1
SCL
CM1
OMSK
SC
TOG2
POUT
T1OUT
SYSCL
/2
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