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参数资料
型号： ATMEGA164A-PU
厂商： Atmel
文件页数： 155/160页
文件大小： 0K
描述： IC MCU AVR 16K 20MHZ 40PDIP
产品培训模块： MCU Product Line Introduction
megaAVR Introduction
标准包装： 14
系列： AVR® ATmega
核心处理器： AVR
芯体尺寸： 8-位
速度： 20MHz
连通性： I²C，SPI，UART/USART
外围设备： 欠压检测/复位，POR，PWM，WDT
输入/输出数： 32
程序存储器容量： 16KB（8K x 16）
程序存储器类型： 闪存
EEPROM 大小： 512 x 8
RAM 容量： 1K x 8
电压 - 电源 (Vcc/Vdd)： 1.8 V ~ 5.5 V
数据转换器： A/D 8x10b
振荡器型： 内部
工作温度： -40°C ~ 85°C
封装/外壳： 40-DIP（0.600"，15.24mm）
包装： 管件
配用： ATSTK600-RC05-ND - STK600 ROUTING CARD AVR
94
8272E–AVR–04/2013
ATmega164A/PA/324A/PA/644A/PA/1284/P
uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source
is selected. The output from the Clock Select logic is referred to as the timer clock (clk
T0).
The double buffered Output Compare Registers (OCR0A and OCR0B) are compared with the
Timer/Counter value at all times. The result of the compare can be used by the Waveform Gen-
erator to generate a PWM or variable frequency output on the Output Compare pins (OC0A and
OC0B). See Section “15.5” on page 95 for details. The Compare Match event will also set the
Compare Flag (OCF0A or OCF0B) which can be used to generate an Output Compare interrupt
request.
15.2.2
Definitions
Many register and bit references in this section are written in general form. A lower case “n”
replaces the Timer/Counter number, in this case 0. A lower case “x” replaces the Output Com-
pare Unit, in this case Compare Unit A or Compare Unit B. However, when using the register or
bit defines in a program, the precise form must be used, that is, TCNT0 for accessing
Timer/Counter0 counter value and so on.
The definitions in Table 15-1 are also used extensively throughout the document.
15.3
Timer/Counter Clock Sources
The Timer/Counter can be clocked by an internal or an external clock source. The clock source
is selected by the Clock Select logic which is controlled by the Clock Select (CS02:0) bits
located in the Timer/Counter Control Register (TCCR0B). For details on clock sources and pres-
caler, see ”Timer/Counter Prescaler” on page 156.
15.4
Counter Unit
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure
15-2 shows a block diagram of the counter and its surroundings.
Figure 15-2. Counter Unit block diagram.
Signal description (internal signals):
Table 15-1.
Definitions.
BOTTOM
The counter reaches the BOTTOM when it becomes 0x00.
MAX
The counter reaches its MAXimum when it becomes 0xFF (decimal 255).
TOP
The counter reaches the TOP when it becomes equal to the highest value in the
count sequence. The TOP value can be assigned to be the fixed value 0xFF
(MAX) or the value stored in the OCR0A Register. The assignment is depen-
dent on the mode of operation.
DATA BUS
TCNTn
Control Logic
count
TOVn
(Int.Req.)
Clock Select
top
Tn
Edge
Detector
( From Prescaler )
clk
Tn
bottom
direction
clear
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