参数资料
型号: ATMEGA324PA-MCH
厂商: Atmel
文件页数: 112/160页
文件大小: 0K
描述: MCU AVR 32KB FLASH 44-VQFN
产品培训模块: MCU Product Line Introduction
megaAVR Introduction
标准包装: 490
系列: AVR® ATmega
核心处理器: AVR
芯体尺寸: 8-位
速度: 20MHz
连通性: I²C,SPI,UART/USART
外围设备: 欠压检测/复位,POR,PWM,WDT
输入/输出数: 32
程序存储器容量: 32KB(16K x 16)
程序存储器类型: 闪存
EEPROM 大小: 1K x 8
RAM 容量: 2K x 8
电压 - 电源 (Vcc/Vdd): 1.8 V ~ 5.5 V
数据转换器: A/D 8x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 44-VQFN 裸露焊盘
包装: 托盘
配用: ATSTK600-ND - DEV KIT FOR AVR/AVR32
55
8272E–AVR–04/2013
ATmega164A/PA/324A/PA/644A/PA/1284/P
11.3
Watchdog Timer
11.3.1
Features
Clocked from separate On-chip Oscillator
Three operating modes
–Interrupt
– System Reset
– Interrupt and System Reset
Selectable Time-out period from 16ms to 8s
Possible Hardware fuse Watchdog always on (WDTON) for fail-safe mode
11.3.2
Overview
Atmel ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P has an Enhanced Watch-
dog Timer (WDT). The WDT is a timer counting cycles of a separate on-chip 128kHz oscillator.
The WDT gives an interrupt or a system reset when the counter reaches a given time-out value.
In normal operation mode, it is required that the system uses the WDR - Watchdog Timer Reset
- instruction to restart the counter before the time-out value is reached. If the system doesn't
restart the counter, an interrupt or system reset will be issued.
Figure 11-7. Watchdog Timer.
In Interrupt mode, the WDT gives an interrupt when the timer expires. This interrupt can be used
to wake the device from sleep-modes, and also as a general system timer. One example is to
limit the maximum time allowed for certain operations, giving an interrupt when the operation
has run longer than expected. In System Reset mode, the WDT gives a reset when the timer
expires. This is typically used to prevent system hang-up in case of runaway code. The third
mode, Interrupt and System Reset mode, combines the other two modes by first giving an inter-
rupt and then switch to System Reset mode. This mode will for instance allow a safe shutdown
by saving critical parameters before a system reset.
The Watchdog always on (WDTON) fuse, if programmed, will force the Watchdog Timer to Sys-
tem Reset mode. With the fuse programmed the System Reset mode bit (WDE) and Interrupt
mode bit (WDIE) are locked to 1 and 0 respectively. To further ensure program security, altera-
tions to the Watchdog set-up must follow timed sequences. The sequence for clearing WDE and
changing time-out configuration is as follows:
128kHz
OSCILLATOR
OSC/2K
OSC/4K
OSC/8K
OSC/16K
OSC/32K
OSC/64K
OSC/128K
OSC/256K
OSC/512K
OSC/1024K
WDP0
WDP1
WDP2
WDP3
WATCHDOG
RESET
WDE
WDIF
WDIE
MCU RESET
INTERRUPT
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