参数资料
型号: ATMEGA324PA-MCH
厂商: Atmel
文件页数: 45/160页
文件大小: 0K
描述: MCU AVR 32KB FLASH 44-VQFN
产品培训模块: MCU Product Line Introduction
megaAVR Introduction
标准包装: 490
系列: AVR® ATmega
核心处理器: AVR
芯体尺寸: 8-位
速度: 20MHz
连通性: I²C,SPI,UART/USART
外围设备: 欠压检测/复位,POR,PWM,WDT
输入/输出数: 32
程序存储器容量: 32KB(16K x 16)
程序存储器类型: 闪存
EEPROM 大小: 1K x 8
RAM 容量: 2K x 8
电压 - 电源 (Vcc/Vdd): 1.8 V ~ 5.5 V
数据转换器: A/D 8x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 44-VQFN 裸露焊盘
包装: 托盘
配用: ATSTK600-ND - DEV KIT FOR AVR/AVR32
139
8272E–AVR–04/2013
ATmega164A/PA/324A/PA/644A/PA/1284/P
temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit
16.12.11 ICR3H and ICR3L – Input Capture Register 3
The Input Capture is updated with the counter (TCNT3) value each time an event occurs on the
ICPn pin (or optionally on the Analog Comparator output for Timer/Counter3). The Input Capture
can be used for defining the counter TOP value.
The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read
simultaneously when the CPU accesses these registers, the access is performed using an 8-bit
temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit
16.12.12 TIMSK1 – Timer/Counter1 Interrupt Mask Register
Bit 7:6 – Reserved
These bits are unused and will always read as zero.
Bit 5 – ICIE1: Timer/Counter1, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt
Vector (see “Interrupts” on page 61) is executed when the ICF1 Flag, located in TIFR1, is set.
Bit 4:3 – Reserved
These bits are unused and will always read as zero.
Bit 2 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Output Compare B Match interrupt is enabled. The corresponding
Interrupt Vector (see “Interrupts” on page 61) is executed when the OCF1B Flag, located in
TIFR1, is set.
Bit 1 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Output Compare A Match interrupt is enabled. The corresponding
Interrupt Vector (see “Interrupts” on page 61) is executed when the OCF1A Flag, located in
TIFR1, is set.
Bit
76543210
(0x97)
ICR3[15:8]
ICR3H
(0x96)
ICR3[7:0]
ICR3L
Read/Write
R/W
Initial Value
00000000
Bit
7
65
43
2
1
0
–ICIE1
OCIE1B
OCIE1A
TOIE1
TIMSK1
Read/Write
R
R/W
R
R/W
Initial Value
0
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