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| 型号： | AUIRF7640S2TR1 |
| 厂商： | International Rectifier |
| 文件页数： | 7/11页 |
| 文件大小： | 0K |
| 描述： | MOSFET N-CH 60V 77A DIRECTFET-S2 |
| 标准包装： | 1,000 |
| 系列： | HEXFET® |
| FET 型： | MOSFET N 通道，金属氧化物 |
| FET 特点： | 标准 |
| 漏极至源极电压(Vdss)： | 60V |
| 电流 - 连续漏极(Id) @ 25° C： | 77A |
| 开态Rds（最大）@ Id, Vgs @ 25° C： | 36 毫欧 @ 13A，10V |
| Id 时的 Vgs(th)（最大）： | 5V @ 25µA |
| 闸电荷(Qg) @ Vgs： | 11nC @ 10V |
| 输入电容 (Ciss) @ Vds： | 450pF @ 25V |
| 功率 - 最大： | 2.4W |
| 安装类型： | 表面贴装 |
| 封装/外壳： | DirectFET? 等距 SB |
| 供应商设备封装： | DIRECTFET SB |
| 包装： | 带卷 (TR) |
AUIRF7640S2TR/TR1
40
30
20
10
TOP Single Pulse
BOTTOM 1% Duty Cycle
ID = 13A
Notes on Repetitive Avalanche Curves , Figures 16, 17:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of T jmax . This is validated for
every part type.
2. Safe operation in Avalanche is allowed as long asT jmax is
not exceeded.
3. Equation below based on circuit and waveforms shown in
Figures 18a, 18b.
4. P D (ave) = Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. I av = Allowable avalanche current.
7. Δ T = Allowable rise in junction temperature, not to exceed
0
25
50 75 100 125 150
Starting TJ , Junction Temperature (°C)
175
T jmax (assumed as 25°C in Figure 16, 17).
t av = Average time in avalanche.
D = Duty cycle in avalanche = t av ·f
Z thJC (D, t av ) = Transient thermal resistance, see figure 11)
Fig 17. Maximum Avalanche Energy Vs. Temperature
15V
P D (ave) = 1/2 ( 1.3·BV·I av ) = D T/ Z thJC
I av = 2 D T/ [1.3·BV·Z th ]
E AS (AR) = P D (ave) ·t av
V (BR)DSS
tp
VDS
L
DRIVER
V GS
RG
20V
tp
D.U.T
IAS
0.01 Ω
+
- VDD
A
I AS
Fig 18a. Unclamped Inductive Test Circuit
Fig 18b. Unclamped Inductive Waveforms
Id
Vds
0
DUT
L
VCC
Vgs
1K
20K
S
Vgs(th)
Fig 19a. Gate Charge Test Circuit
V DS
R D
Qgodr Qgd Qgs2 Qgs1
Fig 19b. Gate Charge Waveform
R G
V GS
D.U.T.
+
-
V DD
V DS
90%
10V
Pulse Width ≤ 1 μs
Duty Factor ≤ 0.1 %
10%
V GS
t d(on)
t r
t d(off)
t f
Fig 20a. Switching Time Test Circuit
www.irf.com
Fig 20b. Switching Time Waveforms
7
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