● Operation of Each Block
? AMP
This is an error amp that functions by comparing the reference voltage (0.65V) with Vo to drive the output Nch FET
(Ron=65m ? ). Frequency optimization helps to realize rapid transit response, and to support the use of functional polymer
output capacitors. AMP input voltage ranges from GND to 2.7V, while the AMP output ranges from GND to VCC. When EN
is OFF, or when UVLO is active, output goes LOW and the output NchFET switches OFF.
? EN
The EN block controls the regulator ON/OFF pin by means of the logic input pin. In OFF position, circuit voltage is
maintained at 0 μ A, thus minimizing current consumption at standby. The FET is switched ON to enable discharge of the
NRCS pin Vo, thereby draining the excess charge and preventing the load IC from malfunctioning. Since no electrical
connection is required (such as between the VCC pin and the ESD prevention Di), module operation is independent of the
input sequence.
? UVLO
To prevent malfunctions that can occur when there is a momentary decrease in VCC supply voltage, the UVLO circuit
switches output OFF, and, like the EN block, discharges the NRCS Vo. Once the UVLO threshold voltage (TYP3.80V) is
exceeded, the power-on reset is triggered and output begins.
? CURRENT LIMIT
With output ON, the current limit function monitors internal IC output current against the parameter value (3.0A). When
current exceeds this level, the current limit module lowers the output current to protect the load IC. When the overcurrent
state is eliminated, output voltage is restored at the parameter value.
? NRCS
The soft start function is realized by connecting an NRCS pin external capacitor to the target ground. Output ramp-up can
be set for any period up to the time the NRCS pin reaches VFB (0.65V). During startup, the NRCS pin serves as the 20 μ A
(TYP) constant current source and charges the externally connected capacitor.
? TSD (Thermal Shut Down)
The shutdown (TSD) circuit automatically switches output OFF when the chip temperature gets too high, thus serving to
protect the IC against “thermal runaway” and heat damage. Because the TSD circuit is provided to shut down the IC in the
presence of extreme heat, in order to avoid potential problems with the TSD, it is crucial that the Tj (max) parameter not be
exceeded in the thermal design.
? VIN
The VIN line is the major current supply line, and is connected to the output NchFET drain. Since no electrical connection
(such as between the VCC pin and an ESD protective Di) is necessary, VIN operates independent of the input sequence.
However, since there is an output NchFET body Di between VIN and Vo, a VIN-Vo electric (Di) connection is present. Note,
therefore, that when output is switched ON or OFF, reverse current may flow to the VIN from Vo.