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参数资料
| 型号： | BR34E02FVT-WE2 |
| 厂商： | Rohm Semiconductor |
| 文件页数： | 12/19页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM SPD 2KB I2C 8TSSOP |
| 标准包装： | 3,000 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 2K (256 x 8) |
| 速度： | 400kHz |
| 接口： | I²C，2 线串口 |
| 电源电压： | 1.7 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-TSSOP |
| 供应商设备封装： | 8-TSSOP |
| 包装： | 带卷 (TR) |
BR34E02FVT-W, BR34E02NUX-W
Technical Note
● WP effective timing
WP is normally fixed at "H" or "L". However, in case WP needs to be controlled in order to cancel the Write command, pay
attention to “WP effective timing” as follows:
The Write command is canceled by setting WP to "H" within the WP cancellation effective period.
The period from the START condition to the rising edge of the clock (which takes in the data DO - the first byte of the Page
Write data) is the ‘invalid cancellation period’. WP input is considered inconsequential during this period. The setup time for
the rising edge of the SCL, which takes in DO, must be more than 100ns.
The period from the rising edge of SCL (which takes in the data D0) to the end of internal write cycle (tWR) is the ‘effective
cancellation period’. When WP is set to "H" during tWR, Write operation is stopped, making it necessary to rewrite the data.
It is not necessary to wait for tWR (5ms max.) after stopping the Write command by WP because the device is in standby
mode.
? The
rising edge of the clock
which take in D0
SCL
? The rising edge
? of SDA
SCL
SDA
D1
D0
ACK
SDA
D0
ACK
AN ENLARGEMENT
AN ENLARGEMENT
A
T
C WORD
K
SDA
S
SLAVE
A
R ADDRESS L ADDRESS
T
A A
C C
K D7 D6 D5 D4 D3 D2 D1 D0 K
L L
DATA
A
C
K
L
S
T
O
P
tWR
WP cancellation
WP cancellation
Stop of the write
WP
invalid period
effective period
operation
Data is not
No data will be written
guaranteed
Fig.41 WP effective timing
● Command cancellation from the START and STOP conditions
Command input is canceled by successive inputs of START and STOP conditions. (Refer to Fig.42)
However, during ACK or data output, the device may set the SDA line to Low, making operation of the START and STOP
conditions impossible, and thus preventing reset. In this case execute reset by software. (Refer to Fig.39)
The internal address counter will not be determined when operating the Cancel command by the START and STOP
conditions during Random, Sequential or Current Read. Operate a Random Read in this case.
SCL
SDA
1
0
1
0
START
CONDITION
STOP
CONDITION
Fig.42 Command cancellation by the START and STOP conditions during input of the Slave Address
www.rohm.com
? 2009 ROHM Co., Ltd. All rights reserved.
12/18
2009.09 - Rev.B
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相关代理商/技术参数 |
参数描述 |
|---|---|
| BR34E02FVT-WTR | 制造商:ROHM 制造商全称:Rohm 功能描述:DDR/DDR2 (For memory module) SPD Memory |
| BR34E02NUX-3E2 | 制造商:ROHM 制造商全称:Rohm 功能描述:Serial EEPROM Series Standard EEPROM Plug & Play EEPROM |
| BR34E02NUX-3TR | 制造商:ROHM 制造商全称:Rohm 功能描述:Serial EEPROM Series Standard EEPROM Plug & Play EEPROM |
| BR34E02NUX-W | 制造商:ROHM Semiconductor 功能描述: |
| BR34E02NUX-WE2 | 制造商:ROHM 制造商全称:Rohm 功能描述:DDR/DDR2 (For memory module) SPD Memory |
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