参数资料
型号: BR34E02FVT-WE2
厂商: Rohm Semiconductor
文件页数: 9/19页
文件大小: 0K
描述: IC EEPROM SPD 2KB I2C 8TSSOP
标准包装: 3,000
格式 - 存储器: EEPROMs - 串行
存储器类型: EEPROM
存储容量: 2K (256 x 8)
速度: 400kHz
接口: I²C,2 线串口
电源电压: 1.7 V ~ 3.6 V
工作温度: -40°C ~ 85°C
封装/外壳: 8-TSSOP
供应商设备封装: 8-TSSOP
包装: 带卷 (TR)
BR34E02FVT-W, BR34E02NUX-W
Technical Note
? With this command the data is programmed into the indicated word address.
? When the Master generates a STOP condition, the device begins the internal write cycle to the nonvolatile memory
array.
? Once programming is started no commands are accepted for tWR (5ms max.).
? This device is capable of sixteen-byte Page Write operations.
? If the Master transmits more than sixteen words prior to generating the STOP condition, the address counter will “roll
over” and the previously transmitted data will be overwritten.
? When two or more byte of data are input, the four low order address bits are internally incremented by one after the
receipt of each word, while the four higher order bits of the address (WA7 ~ WA4) remain constant.
○ Read Cycle
During Read Cycle operation data is read from the EEPROM. The Read Cycle is composed of Random Read Cycle and
Current Read Cycle. The Random Read Cycle reads the data in the indicated address.
The Current Read Cycle reads the data in the internally indicated address and verifies the data immediately after the
Write Operation. The Sequential Read operation can be performed with both Current Read and Random Read. With the
Sequential Read Cycle it is possible to continuously read the next data.
It is necessary to input
SDA
L IN E
S
T
A
R
T
SLAVE
ADDRESS
1 0 1 0 A 2 A 1 A 0
W
R
I
T
E
WA
7
W ORD
A D D R E S S (n )
WA
0
S
T
A
R
T
SLAVE
ADDRESS
1 0 1 0 A 2 A 1 A 0
R
E
A
D
D7
D A TA (n)
“High” at last ACK timing.
S
T
O
P
D0
R A
/ C
W K
A
C
K
R A
/ C
W K
A
C
K
Fig.35 Random Read Cycle Timing
S
T
R
S
A
R
T
SLAVE
ADDRESS
E
A
D
DATA
T
O
P
It is necessary to input
“High” at last ACK timing.
SDA
LINE
1 0 1 0 A2 A1 A0
R A
C
/
W K
D7
D0
A
C
K
Fig.36 Current Read Cycle Timing
? Random Read operation allows the Master to access any memory location indicated by word address.
? In cases where the previous operation is Random or Current Read (which includes Sequential Read), the internal
address counter is increased by one from the last accessed address (n). Thus Current Read outputs the data of the
next word address (n+1).
? If an Acknowledge is detected and no STOP condition is generated by the Master (μ-COM), the device will continue to
transmit data. (It can transmit all data (2kbit 256word))
? If an Acknowledge is not detected, the device will terminate further data transmissions and await a STOP condition
before returning to standby mode.
? If an Acknowledge is detected with the "Low" level (not "High" level), the command will become Sequential Read, and
the next data will be transmitted. Therefore, the Read command is not terminated. In order to terminate Read input
Acknowledge with "High" always, then input a STOP condition.
S
T
A
R
T
SLAVE
ADDRESS
R
E
A
D
D A T A (n )
D A T A (n + x)
S
T
O
P
It is necessary to
input “High” at
last ACK timing.
SDA
L IN E
1 0 1 0 A 2 A 1 A 0
R A
/ C
W K
D7
D0
A
C
K
A
C
K
D7
D0
A
C
K
Fig.37
Sequential Read Cycle Timing ( With Current Read )
www.rohm.com
? 2009 ROHM Co., Ltd. All rights reserved.
9/18
2009.09 - Rev.B
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