- 您现在的位置：买卖IC网 > PDF目录256019 > BU-61840B3-100L (DATA DEVICE CORP) 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, PBGA128 PDF资料下载
参数资料
| 型号： | BU-61840B3-100L |
| 厂商： | DATA DEVICE CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, PBGA128 |
| 封装： | 0.815 X 0.815 INCH, 0.140 INCH HEIGHT, BGA-128 |
| 文件页数： | 31/60页 |
| 文件大小： | 763K |
| 代理商： | BU-61840B3-100L |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页当前第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页
37
Data Device Corporation
www.ddc-web.com
BU-6174X/6184X/6186X
D-03/02-250
2, 6
3, 4, 5, 7
6
2
2, 6
7, 8
6, 9
3, 4, 5, 7
6
6, 9
7, 8, 9
3, 4, 5, 7
6
3, 4, 5, 7
2, 6
MAX
TYP
MIN
UNITS
MAX
TYP
MIN
DESCRIPTION
REF
4.4
155
555
655
138
430
2.8
3.7
35
27
62
45
61
44
40
0
40
0
40
∞
40
0
25
355
35
165
150
135
265
250
235
205
187.5
170
30
23
11
315
300
285
30
15
40
12
16
10
2.2
105
15
NOTES
2, 9
2, 6
117
s
7.2
(contended access, with ENHANCED CPU ACCESS = “0” @ 10 MHz)
ns
150
(uncontended access @ 10 MHz)
ns
550
(contended access, with ENHANCED CPU ACCESS = “1” @ 12 MHz)
ns
650
(contended access, with ENHANCED CPU ACCESS = “1” @ 10 MHz)
ns
133
(uncontended access @ 12 MHz)
ns
425
(contended access, with ENHANCED CPU ACCESS = “1” s @ 16 MHz)
s
4.6
(contended access, with ENHANCED CPU ACCESS = “0” @ 16 MHz)
s
6.0
(contended access, with ENHANCED CPU ACCESS = “0” @ 12 MHz)
ns
40
@ 10 MHz
t3
t4
ns
32
@ 12 MHz
ns
67
@ 10 MHz
ns
50
@ 12 MHz
ns
71
@ 10 MHz
ns
54
@ 12 MHz
ns
40
CLOCK IN rising edge delay to output data valid
t19
ns
0
STRBD high hold time from READYD rising
t18
ns
40
STRBD rising delay to output data tri-state
t17
ns
0
Output Data hold time following STRBD rising edge
t16
ns
30
STRBD rising edge delay to IOEN rising edge and READYD rising edge
t15
ns
∞
READYD falling to STRBD rising release time
t14
ns
40
CLOCK IN rising edge delay to READYD falling
t13
t12
ns
0
SELECT hold time following IOEN falling
t6
ns
30
@ 16 MHz
ns
350
(contended access, with ENHANCED CPU ACCESS = “1” @ 20 MHz)
ns
30
Address valid setup time prior to CLOCK IN rising edge
t9
ns
165
150
135
IOEN falling delay to READYD falling (@ 20 MHz)
ns
265
250
235
@ 12 MHz
ns
205
187.5
170
@ 16 MHz
ns
30
MEM/REG, RD/WR hold time following CLOCK IN falling edge
t8
ns
33
@ 16 MHz
ns
21
Output Data valid prior to READYD falling (@ 20 MHz)
ns
315
300
285
@ 10 MHz
ns
30
Address hold time following CLOCK IN rising edge
t10
t11
ns
10
MEM/REG, RD/WR setup time prior to CLOCK IN falling edge
t7
ns
40
CLOCK IN rising edge delay to IOEN falling edge
t5
ns
17
Time for Address to become valid following SELECT and STRBD low (@ 20 MHz)
ns
21
@ 16 MHz
ns
15
Time for MEM/REG and RD/WR to become valid following SELECT and STRBD
low(@ 20 MHz)
s
3.6
(contended access, with ENHANCED CPU ACCESS = “0” @ 20 MHz)
ns
100
SELECT and STRBD low to IOEN low (uncontended access @ 20 MHz)
t2
ns
10
SELECT and STRBD low setup time prior to clock rising edge
t1
3.3V LOGIC
5V LOGIC
TABLE FOR FIGURE 13. CPU READING RAM OR REGISTERS
(SHOWN FOR 16-BIT, BUFFERED, NONZERO WAIT MODE)
ns
112
(uncontended access @ 16 MHz)
相关PDF资料 |
PDF描述 |
|---|---|
| BU-61840B3-300Y | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, PBGA128 |
| BU-61860B3-102 | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, PBGA128 |
| BU-61860B3-402W | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, PBGA128 |
| BU-61860B4-100Z | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, PBGA128 |
| BU-61860B4-200S | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, PBGA128 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| BU-61840B3NEW | 制造商:未知厂家 制造商全称:未知厂家 功能描述:MIL-STD-1553 Components |μ-ACE (Micro-ACE?) |
| BU-61843 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:MIL-STD-1553 Components |Enhanced Mini-ACE? |
| BU-61843F3-100 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Telecommunication IC |
| BU-61843F3-110 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Telecommunication IC |
| BU-61843F4-100 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Telecommunication IC |
发布紧急采购，3分钟左右您将得到回复。