参数资料
型号: BU-61840B3-100L
厂商: DATA DEVICE CORP
元件分类: 微控制器/微处理器
英文描述: 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, PBGA128
封装: 0.815 X 0.815 INCH, 0.140 INCH HEIGHT, BGA-128
文件页数: 40/60页
文件大小: 763K
代理商: BU-61840B3-100L
45
Data Device Corporation
www.ddc-web.com
BU-6174X/6184X/6186X
D-03/02-250
A15 / CLK_SEL_1
A15
66
For BU-6186X (64K RAM versions), this signal is always config-
ured as address line A15 (MSB). Refer to the description for A11-
A0 below.
For BU-6184X/6174X (4K RAM versions), if UPADDREN is con-
nected to logic "1", this signal operates as address line A15.
For BU-6184X/6174X (4K RAM versions), if UPADDREN is con-
nected to logic "0", this signal operates as CLK_SEL_1. In this
case, A15/CLK_SEL_1 and A14/CLK_SEL_0 are used to select
the Enhanced Mini-ACE's clock frequency, as follows:
Clock
CLK_SEL_1
CLK_SEL_0
Frequency
0
10 MHz
0
1
20 MHz
1
0
12 MHz
1
16 MHz
A11
A14 / CLK_SEL_0
A14
8
For BU-6186X (64K RAM versions), this signal is always config-
ured as address line A14. Refer to the description of A11-A0
below.
For BU-6184X/6174X (4K RAM versions), if UPADDREN is con-
nected to logic "1", this signal operates as A14.
For BU-6184X/6174X (4K RAM versions), if UPADDREN is con-
nected to logic "0", then this signal operates as CLK_SEL_1. In
this case, CLK_SEL_1 and CLK_SEL_0 are used to select the
Enhanced Mini-ACE's clock frequency, as defined in the descrip-
tion for A15/CLK_SEL1 above.
B10
A13 / Vcc -LOGIC
71
For BU-6186X (64K RAM versions), this signal is always config-
ured as address line A13. Refer to the description for A11-A0
below.
For BU-6184X/6174X (4K RAM versions), if UPADDREN is con-
nected to logic "1", this signal operates as A13.
For BU-6184X/6174X (4K RAM versions), if UPADDREN is con-
nected to logic "0", then this signal MUST be connected to
+5V/+3.3V-LOGIC (logic "1").
A10
A13
TABLE 50. PROCESSOR ADDRESS BUS
SIGNAL NAME
DESCRIPTION
BU-6186XFX/GX
BU-6184XFX/GX
BU-6174XFX/GX
BALL
PIN
4K RAM
64K RAM
BU-61860BX
BU-61840BX
BU-61740BX
相关PDF资料
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