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参数资料
| 型号： | BU9880GUL-WE2 |
| 厂商： | Rohm Semiconductor |
| 文件页数： | 17/25页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM 64KBIT 2WIRE VCSP50L1 |
| 标准包装： | 3,000 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 64K (8K x 8) |
| 速度： | 400kHz |
| 接口： | I²C，2 线串口 |
| 电源电压： | 1.7 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 6-UFBGA，CSPBGA |
| 供应商设备封装： | VCSP50L1 |
| 包装： | 带卷 (TR) |
BU9880GUL-W (64Kbit)
Datasheet
● WP valid timing (write cancel)
WP is usually fixed to 'H' or 'L', but when WP is used to cancel write cycle and so forth, pay attention to the following WP
valid timing. During write cycle execution, in cancel valid area, by setting WP='H', write cycle can be cancelled. In both byte
write cycle and page write cycle, the area from the first start condition of command to the rise of clock to taken in D0 of
data(in page write cycle, the first byte data) is cancel invalid area.
WP input in this area becomes Don't care. Set the setup time to rise of D0 taken 100ns or more. The area from the rise of
SCL to take in D0 to the end of internal automatic write (tWR) is cancel valid area. And, when it is set WP='H' during tWR,
write is ended forcibly, data of address under access is not guaranteed, therefore, write it once again.(Refer to Figure 39.)
After execution of forced end by WP standby status gets in, so there is no need to wait for tWR (5ms at maximum).
? Rise of D0 taken clock
SCL
SCL
? Rise of SDA
SDA
D1
D0
ACK
SDA
D0
ACK
Enlarged view
Enlarged view
C D7 D6 D5 D4 D3 D2 D1 D0
SDA
S
T
A
R
T
Slave
address
A A
C Word
K address K
L L
A
C
K
L
Data
A
C
K
L
S
T
O
P
tWR
WP
WP cancel invalid area
WP cancel valid area
Data is not written.
Write forced end
Data not guaranteed
Figure 39. WP valid timing
● Command cancel by start condition and stop condition
During command input, by continuously inputting start condition and stop condition, command can be cancelled. (Refer to
Figure 40.) However, in ACK output area and during data read, SDA bus may output 'L', and in this case, start condition and
stop condition cannot be input, so reset is not available. Therefore, execute software reset. And when command is
cancelled by start, stop condition, during random read cycle, sequential read cycle, or current read cycle, internal setting
address is not determined, therefore, it is not possible to carry out current read cycle in succession. When to carry out read
cycle in succession, carry out random read cycle.
SCL
SDA
1
0
1
0
Start condition
Stop condition
Figure 40. Case of cancel by start, stop condition during slave address input
www.rohm.com
? 2012 ROHM Co., Ltd. All rights reserved.
TSZ22111 ? 15 ? 001
17/22
TSZ02201-0R2R0G100340-1-2
21.AUG.2012 Rev.001
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相关代理商/技术参数 |
参数描述 |
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| BU9881 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:I2C Serial EEPROM |
| BU9881F | 制造商:未知厂家 制造商全称:未知厂家 功能描述:I2C Serial EEPROM |
| BU9882FV-W | 制造商:ROHM 制造商全称:Rohm 功能描述:EDID Memory (For display) |
| BU9882FV-WE2 | 功能描述:电可擦除可编程只读存储器 2K BIT 128 X 8 X 2 3.3V/5V 14PIN RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 |
| BU9882F-W | 制造商:ROHM 制造商全称:Rohm 功能描述:EDID Memory (For display) |
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