参数资料
型号: BU9880GUL-WE2
厂商: Rohm Semiconductor
文件页数: 3/25页
文件大小: 0K
描述: IC EEPROM 64KBIT 2WIRE VCSP50L1
标准包装: 3,000
格式 - 存储器: EEPROMs - 串行
存储器类型: EEPROM
存储容量: 64K (8K x 8)
速度: 400kHz
接口: I²C,2 线串口
电源电压: 1.7 V ~ 5.5 V
工作温度: -40°C ~ 85°C
封装/外壳: 6-UFBGA,CSPBGA
供应商设备封装: VCSP50L1
包装: 带卷 (TR)
BU9880GUL-W (64Kbit)
● Sync Data Input / Output Timing
Datasheet
SCL
tR
tF
tHIGH
SCL
tHD :STA
tSU :DAT
tLOW
tHD :DAT
DATA(1)
DATA(n)
SDA
(Input)
tBUF
tPD
tDH
SDA
D1
D0
ACK
ACK
tWR
SDA
(Output)
○ Input read at the rise edge of SCL
○ Data output in sync with the fall of SCL
WP
tSU : WP
Stop condition
tHD : WP
SCL
Figure 1-(a) Sync data input / output timing
Figure 1-(d) WP timing at write execution
tSU :STA
tHD :STA
tSU :STO
SCL
DATA(1)
DATA(n)
SDA
START BIT
STOP BIT
SDA
D1
D0
ACK
tHIGH:WP
ACK
tWR
WP
Figure 1-(b) Start - stop bit timing
At write execution, in the area from the D0 taken clock rise
of the first DATA(1), to tWR, set WP= 'LOW'.
By setting WP "HIGH" in the area, write can be cancelled.
SCL
When it is set WP = 'HIGH' during tWR, write is forcibly ended,
and data of address under access is not guaranteed, therefore write it
once again.
SDA D0
WRITE DATA(n)
ACK
STOP
CONDITION
t WR
START
CONDITION
Figure 1-(e) WP timing at write cancel
Figure 1-(c) Write cycle timing
www.rohm.com
? 2012 ROHM Co., Ltd. All rights reserved.
TSZ22111 ? 15 ? 001
3/22
TSZ02201-0R2R0G100340-1-2
21.AUG.2012 Rev.001
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