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参数资料
| 型号： | BU9883FV-WE2 |
| 厂商： | Rohm Semiconductor |
| 文件页数： | 16/28页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM 6KBIT 400KHZ SSOP16 |
| 标准包装： | 2,500 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 6K（256 x 8 x 3） |
| 速度： | 400kHz |
| 接口： | I²C，2 线串口 |
| 电源电压： | 3 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 16-SSOPB |
| 包装： | 带卷 (TR) |
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BU9883FV-W
Datasheet
S
T
A
R
T
SLAVE
ADDRESS
W
R
I
T
E
1st WORD
ADDRESS(n)
DATA(n)
DATA(n+7)
S
T
O
P
SDA
LINE
1 0 1
0
0
P1 P0
WA7
WA0
D7
D0
D0
R
/
W
A
C
K
A
C
K
A
C
K
A
C
K
WPB
Figure 40. PAGE WRITE CYCLE TIMING (PORT0)
○ This device is capable of eight byte page write operation.
○ After the receipt of each word, the three low order address bits are internally incremented by one. The most
significant address bits (WA7 to WA3) remain constant, if the master transmits more than 8 words.
○ The relationship of P1, P0 inputs and access BANK is described as follows.
P1
0
0
1
1
P0
0
1
0
1
BANK
No opearation
BANK1
BANK2
BANK3
○ Don't set P1, P0=0, 0. If P1, P0 are set to 0, there is no target bank, so this device doesn't return acknowledge.
○ WPB terminal must be set to “HIGH” during Byte Write cycle, and Page Write cycle, and internal Write cycles. If WPB is
set to “LOW” in above condition, programing doesn't work, and during internal Write cycle, WPB terminal set to “LOW”,
this device terminate programing, and the data in programing address is not stored correctly.
S
T
A
R
T
SLAVE
ADDRESS
W
R
I
T
E
1st WORD
ADDRESS(n)
S
T
A
R
T
SLAVE
ADDRESS
R
E
A
D
DATA(n)
S
T
O
P
SDA
LINE
1
0 1 0
0
P1 P0
WA7
WA0
1
0 1 0
0
P1 P0
D7
D0
R
/
W
A
C
K
A
C
K
R A
/ C
W K
A
C
K
WPB
Figure 41. RANDOM READ CYCLE TIMING （ PORT0 ）
○ Random read operation allows the master to access any memory location which is appointed by P1, P0 bit. This
operation
involves a two-step process. First, the master issue a write command which includes the start condition and the slave
address field (with R/W set to “0”) followed by the address of the word be read.
○ This procedure sets the internal address counter of this device to the desired address. After the word address
acknowledge is received by the master, the master immediately reissues a start condition followed by the slave address
field with R/W the set to “1.” This device will respond with an acknowledge and then transmit the 8-data bits stored at the
addressed location.
If the master does not acknowledge the transmission but does generate the stop condition, at this point this device
discontinues transmission.
S
T
A
R
T
SLAVE
ADDRESS
R
E
A
D
DATA
S
T
O
P
SDA
LINE
1
0
1
0
0 P1 P0
D7
D0
R A
/ C
W K
A
C
K
WPB
Figure 42. CURRENT READ CYCLE TIMING (PORT0)
www.rohm.com
? 2012 ROHM Co., Ltd. All rights reserved.
TSZ22111 ? 15 ? 001
16/25
TSZ02201-0R2R0G100420-1-2
31.AUG.2012 Rev.001
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相关代理商/技术参数 |
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| BU9888FV-W | 制造商:ROHM 制造商全称:Rohm 功能描述:High Reliability Serial EEPROMs |
| BU9888FV-WE2 | 制造商:ROHM 制造商全称:Rohm 功能描述:High Reliability Serial EEPROMs |
| BU9889GUL-W | 制造商:ROHM 制造商全称:Rohm 功能描述:WL-CSP EEPROM family I2C BUS |
| BU9889GUL-WE2 | 功能描述:电可擦除可编程只读存储器 电可擦除可编程只读存储器 Serial-2Wire 8Kb RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 |
| BU9890GUL-W | 制造商:ROHM 制造商全称:Rohm 功能描述:Silicon Monolithic Integrated Circuit |
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