参数资料
型号: BU9883FV-WE2
厂商: Rohm Semiconductor
文件页数: 18/28页
文件大小: 0K
描述: IC EEPROM 6KBIT 400KHZ SSOP16
标准包装: 2,500
格式 - 存储器: EEPROMs - 串行
存储器类型: EEPROM
存储容量: 6K(256 x 8 x 3)
速度: 400kHz
接口: I²C,2 线串口
电源电压: 3 V ~ 5.5 V
工作温度: -40°C ~ 85°C
封装/外壳: 16-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 16-SSOPB
包装: 带卷 (TR)
BU9883FV-W
Datasheet
○ When the command just before Current Read cycle is Random Read cycle or Current Read cycle (each including
Sequential Read cycle), data of incremented last read address (n)-th address, i.e.n, data of the (n+1)-th address is output.
When the command just before Current Read cycle is Byte Write or Page write, data of latest write address is output.
○ Random read operation allows the master to access any memory location. The BANK which is appointed by P1, P0. This
operation involves a two-step process.
First, the master issues a write command which includes the start condition and the slave address field (with R/W set to
“0”) followed by the address of the word be read. This procedure sets the internal address counter of this device to the
desired address. After the word address acknowledge is received by the master, the master immediately reissues a
start condition followed by the slave address field with R/W the set to “1.” This device will respond with an acknowledge
and then transmit the 8-data bits stored at the addressed location.
If the master does not acknowledge the transmission but does generate the stop condition, at this point this device
discontinues transmission.
note)If the master send Acknowredge at after D0 output, Sequential Read is selected, and this device output next address data, and master can't send stop
condition, so master can't discontinues transmission. To stop read command, the master must send no Acknowledge at after D0 output, and issue stop
condition.
S
T
A
R
T
SLAVE
ADDRESS
R
E
A
D
DATA(n)
DATA(n+x)
S
T
O
P
SDA
LINE
1 0 1 0
0
0 0
D7
D0
D7
D0
※1 R
/
W
A
C
K
A
C
K
A
C
K
A
C
K
WPB
Figure 46. SEQUENTIAL READ CYCLE TIMING ( PORT1 to 3 )
○ During the sequential read operation, the internal address counter of this device automatically increments with each
acknowledge received ensuring the data from address n will be followed with the data from n+1. For read operations, all
bits of the address counter are incremented allowing the entire array to be read during a single operation. When the
counter reaches the top of the array, it will “roll over to the bottom of the array and continue to transmit the data.
○ The sequential read operation can be performed with both current read and random read.
● Access Control of PORT0,1,2,3
WPB terminal controls access enable of each PORT, as follows.
PORT
WPB terminal inputs
0 1
PORT0 not accessible Read/Write
PORT1 Read not accessible
PORT2 Read not accessible
PORT3 Read not accessible
Table4 WPB terminal and port accesibility
○ When WPB terminal is “HIGH”, PORT0 only can access this device.
In this case, when commands from PORT1, 2, 3 are inputted, these ports don't return acknowledge.
○ When WPB terminal is “LOW”, PORT0 access is not valid, but PORT1, 2, 3 can access this device this device.
Commands from PORT1, 2, 3 is performs independently other port.
www.rohm.com
? 2012 ROHM Co., Ltd. All rights reserved.
TSZ22111 ? 15 ? 001
18/25
TSZ02201-0R2R0G100420-1-2
31.AUG.2012 Rev.001
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