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参数资料
| 型号： | BX80547RE2933CN |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 2930 MHz, MICROPROCESSOR, PBGA775 |
| 封装： | FLIP CHIP, LGA-775 |
| 文件页数： | 14/94页 |
| 文件大小： | 2796K |
| 代理商： | BX80547RE2933CN |
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Datasheet
21
Electrical Specifications
With the implementation of a source synchronous data bus comes the need to specify two sets of
timing parameters. One set is for common clock signals which are dependent upon the rising edge
of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second set is for the source synchronous signals
which are relative to their respective strobe lines (data and address) as well as the rising edge of
BCLK0. Asychronous signals are still present (A20M#, IGNNE#, etc.) and can become active at
any time during the clock cycle. Table 2-3 identifies which signals are common clock, source
synchronous, and asynchronous.
NOTES:
1. Refer to Section 4.2 for signal descriptions.
2. EDRDY# and PC_REQ# are not features of the Celeron D processor in the 775-land package. They are
included here for future processor compatibility.
3. The value of these signals during the active-to-inactive edge of RESET# defines the processor configuration
options. See Section 6.1 for details.
4. PC_REQ# is driven by the processor as Common Clock (1X); however, it must be received at the chipset as
Source Synchronous and associated with ADSTB0#.
5. In processor systems where there is no debug port implemented on the system board, these signals are used
to support a debug port interposer. In systems with the debug port implemented on the system board, these
signals are no connects.
Table 2-3. FSB Signal Groups
Signal Group
Type
Signals1
GTL+ Common Clock Input
Synchronous to
BCLK[1:0]
BPRI#, DEFER#, RS[2:0]#, RSP#, TRDY#, EDRDY#2
GTL+ Common Clock I/O
Synchronous to
BCLK[1:0]
AP[1:0]#, ADS#, BINIT#, BNR#, BPM[5:0]#, BR0#, DBSY#,
DP[3:0]#, DRDY#, HIT#, HITM#, LOCK#, MCERR#
GTL+ Source Synchronous I/O
Synchronous to assoc.
strobe
GTL+ Strobes
Synchronous to
BCLK[1:0]
ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#
GTL+ Asynchronous Input
A20M#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, SMI#,
STPCLK#, RESET#
GTL+ Asynchronous Output
FERR#/PBE#, IERR#, THERMTRIP#
GTL+ Asynchronous Input/Output
PROCHOT#
TAP Input
Synchronous to TCK
TCK, TDI, TMS, TRST#
TAP Output
Synchronous to TCK
TDO
FSB Clock
Clock
BCLK[1:0], ITP_CLK[1:0]5
Power/Other
VCC, VTT, VCCA, VCCIOPLL, VID[7:0], VSS, VSSA,
GTLREF[1:0], COMP[5:0], RESERVED, TESTHI[13:0],
THERMDA, THERMDC, VCC_SENSE, VSS_SENSE,
BSEL[2:0], SKTOCC#, DBR#5, VTTPWRGD, BOOTSELECT,
PWRGOOD, VTT_OUT_LEFT, VTT_OUT_RIGHT, VTT_SEL,
LL_ID[1:0], VID_SELECT, GTLREF_SEL
Signals
Associated Strobe
REQ[4:0]#, A[16:3]#3
PC_REQ#2, 4
ADSTB0#
A[35:17]#3
ADSTB1#
D[15:0]#, DBI0#
DSTBP0#, DSTBN0#
D[31:16]#, DBI1#
DSTBP1#, DSTBN1#
D[47:32]#, DBI2#
DSTBP2#, DSTBN2#
D[63:48]#, DBI3#
DSTBP3#, DSTBN3#
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