参数资料
| 型号： | CC-ACC-ADD-2443 |
| 厂商： | Digi International |
| 文件页数： | 19/148页 |
| 文件大小： | 0K |
| 描述： | BRD AUDIO ADD-0N CC 2443 KIT |
| 标准包装： | 1 |
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Chapter 1
NORMAL mode
IDLE mode
STOP mode
In General Clock Gating mode, the On/Off clock gating of the individual clock
source of each IP block is performed by controlling each corresponding clock source
enable bit. The Clock Gating is applied instantly whenever the corresponding bit is
changed.
In IDLE mode, the clock to the CPU core is stopped. The IDLE mode is activated just
after the execution of the STORE instruction that enables the IDLE Mode bit. The
IDLE Mode bit should be cleared after wake-up from IDLE state.
All clocks are stopped for minimum power consumption. Therefore, the PLL and
oscillator circuits are also stopped (oscillator circuit is controlled by PWRCFG
register). The STOP mode is activated after the execution of the STORE instruction
that enables the STOP mode bit. The STOP Mode bit should be cleared after wake-
up from STOP state.
To exit from STOP mode, external interrupt, RTC alarm, RTC Tick, or BATT_FLT has
to be activated. During the wake-up sequence, the crystal oscillator and PLL may
begin to operate. The crystal oscillator settle-down time and the PLL lock-time is
required for a stable ARMCLK and automatically inserted by the hardware of
S3C2443X. During these lock and settle-down times, no clock is supplied to the
internal logic circuitry.
The following describes the sequence initiating STOP mode:
1
2
3
4
5
6
7
Set the STOP Mode bit (by the main CPU).
System controller requests bus controller to finish pending transaction.
Bus controller sends acknowledgement to system controller after bus
transactions are completed.
System controller requests memory controller to enter self-refresh mode,
preserving SDRAM contents.
System controller waits for self-refresh acknowledgement from memory
controller.
After receiving the self-refresh acknowledge, system controller disables system
clocks, and switches SYSCLK source to MPLL reference clock.
Disables PLLs and Crystal (XTI) oscillation. If OSC_EN_STOP bit in PWRCFG
register is 'high,' then system controller does not disable crystal oscillation.
Note: DRAM has to be in self-refresh mode during STOP and SLEEP mode to retain valid
memory data. LCD must be stopped before STOP and SLEEP mode, because DRAM can
not be accessed when it is in self-refresh mode.
19
ConnectCore 9M 2443 & Wi-9M 2443 Hardware Reference
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