参数资料
| 型号： | CC-ACC-ADD-2443 |
| 厂商： | Digi International |
| 文件页数： | 31/148页 |
| 文件大小： | 0K |
| 描述： | BRD AUDIO ADD-0N CC 2443 KIT |
| 标准包装： | 1 |
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Chapter 1
Port M
Selectable Pin Functions
On module,
default used as
GPM1
GPM0
Input
Input
FRnB
RSMBWAIT
-
-
FRnB
Internal Input
..................................................................................
Interfaces
RTC
UART interface
Instead of using the S3C2443-internal RTC, an external RTC (Dallas D1337) is
implemented on the module to optimize the power consumption characteristics in
sleep modes. Therefore the pin RTCVDD has to be connected to 3.3V and the pin
XTIrtc has also to be connected to 3.3V, while pin XTOrtc has to be left floating. An
external quartz is not necessary, if the internal RTC is not used.
The on-module RTC is connected to the I2C bus and powered by a 3V battery, which
has to be mounted on the base board. If no RTC is used, the pin VRTC at the system
connector can be left floating, because two Schottky diodes are used to power the
RTC either from 3.3V, or from the battery. The state of this battery will not be
supervised on the module.
The on-module RTC is a CMOS real time clock/calendar optimized for low power
consumption. An interrupt output is provided. All address and data are transferred
serially via a two-line bidirectional I2C-bus. Maximum bus speed is 400 kbit/s.
The low active interrupt output (CLK_INT#) of the RTC is connected to interrupt input
EINT7 of the CPU.
The I2C device address of the RTC is 0x68 (bits A7..A1), or 0xD0/0xD1 if expressed in
an 8-bit format, including the R/W bit at the end (bits A7..A1 + R/W bit).
The S3C2443 Universal Asynchronous Receiver and Transmitter (UART) provide four
independent asynchronous serial I/O (SIO) ports, each of which can operate in
Interrupt-based or DMA-based mode. In other words, the UART can generate an
interrupt or a DMA request to transfer data between CPU and the UART. The UART can
support bit rates up to 921.6K bps using system clock. Each UART channel contains
two 64-byte FIFOs for receiver and transmitter.
On the system connector, there are the signals for two UART interfaces provided.
Each interface consists of the data lines RXD/TXD and the handshake lines
RTS#/CTS#. The UARTs are part of the CPU. If the handshake lines of the third UART
interface (RTS2#/CTS2#) are not used, they could be used as data lines for a fourth
UART interface (TXD3/RXD3).
31
ConnectCore 9M 2443 & Wi-9M 2443 Hardware Reference
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