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参数资料
| 型号： | CDB5529 |
| 厂商： | Cirrus Logic Inc |
| 文件页数： | 15/31页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD FOR CS5529 |
| 标准包装： | 1 |
| ADC 的数量： | 1 |
| 位数： | 16 |
| 采样率（每秒）： | 303 |
| 数据接口： | 串行 |
| 输入范围： | ±2.5 V |
| 在以下条件下的电源（标准）： | 2.6mW @ 2.5V |
| 工作温度： | -40°C ~ 85°C |
| 已用 IC / 零件： | CS5529 |
| 已供物品： | 板，线缆，磁盘 |
| 产品目录页面： | 755 (CN2011-ZH PDF) |
| 相关产品： | CS5529-ASZR-ND - IC ADC 16BIT W/6BIT LATCH 20SSOP 598-1110-5-ND - IC ADC 16BIT W/6BIT LATCH 20SSOP |
| 其它名称： | 598-1015 |
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CS5529
22
DS246F5
SDO flag falls. For instance, the user can just read
the conversion data register again to exit the contin-
uous conversion mode.
Note:
1) If the user begins to clear the SDO flag and
read the conversion data, this action must be
finished before the conversion cycle which is
occurring in the background is complete if the
user wants to be able to read the new
conversion data.
2) If a CC command is issued to the converter
while it is performing a conversion, the filter
will stop the current conversion and start a
new convolution cycle to perform a new
conversion.
3) Continuous conversions aren’t allowed
unless the port flag bit is set in the
configuration register.
4) The converter will remain in data mode and
continually perform conversions until the exit
command is issued (i.e. to exit the user must
read a register).
Output Coding
As shown in the Output Conversion Data Register
Descriptions, the CS5529 presents output conver-
sions as a 24-bit conversion word. The first 16 bits
of the conversion word represent conversion data.
The third byte contains two error flag bits.
In the third byte, D7-D4 are always logic 1; D3-D2
are always logic 0; and bits D1-D0 are the two flag
bits. The OF (Overrange Flag) bit is set to a logic 1
any time the input signal is: 1) more positive than
positive full scale, 2) more negative than zero (un-
ipolar mode), 3) more negative than negative full
scale (bipolar mode). It is cleared back to logic 0
whenever a conversion word occurs which is not
overranged.The OD (Oscillation Detect) bit is set to
a logic 1 any time that an oscillatory condition is de-
tected in the modulator. This does not occur under
normal operating conditions, but may occur when-
ever the input to the converter is extremely over-
ranged. If the OD bit is set, the conversion data bits
can be completely erroneous. The OD flag bit will be
cleared to logic 0 when the modulator becomes sta-
ble.
Table 2 and Table 3 illustrate the output coding for
the CS5529. Unipolar conversions are output in bi-
nary format and bipolar conversions are output
two's complement.
D23
D22
D21
D20
D19
D18
D17
D16
D15
D14
D13
D12
MSB
141312
11
10
9
8
7
6
5
4
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
3
2
1
LSB
1
0
OD
OF
Table 2. Output Conversion Data Register Description (16 bits + flags).
Note: VFS in the table equals the voltage between ground and full scale for any of the unipolar gain ranges,
or the voltage between
± full scale for any of the bipolar gain ranges. See text about error flags under
overrange conditions.
Unipolar Input Voltage
Offset Binary
Bipolar Input Voltage
Two's
Complement
>(VFS-1.5 LSB)
FFFF
>(VFS-1.5 LSB)
7FFF
VFS-1.5 LSB
FFFF
-----
FFFE
VFS-1.5 LSB
7FFF
-----
7FFE
VFS/2-0.5 LSB
8000
-----
7FFF
-0.5 LSB
0000
-----
FFFF
+0.5 LSB
0001
-----
0000
-VFS+0.5 LSB
8001
-----
8000
<(+0.5 LSB)
0000
<(-VFS+0.5 LSB)
8000
Table 3. CS5529 16-bit Output Coding.
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