参数资料
| 型号： | CDB8422 |
| 厂商： | Cirrus Logic Inc |
| 文件页数： | 25/46页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR CS8422 RCVR |
| 标准包装： | 1 |
| 主要目的： | 音频，采样率转换器 |
| 嵌入式： | 是，FPGA / CPLD |
| 已用 IC / 零件： | CS8422 |
| 主要属性： | PCM，IEC-60958，AES3/EBU，S/PDIF，以及 XLR 输入，RCA 同轴和光学 S/PDIF 输出 |
| 次要属性： | 28 ~ 216 kHz 采样率范围，输入/输出率范围从 6:1 至 1:6 |
| 已供物品： | 板 |
| 产品目录页面： | 759 (CN2011-ZH PDF) |
| 相关产品： | 598-1732-ND - IC SAMPLE RATE CONVERTER 32QFN |
| 其它名称： | 598-1568 |
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CDB8422
3.3
Hardware Mode Control
This section provides a full description for the hardware mode control switches S3, S4, and S7, see the ta-
bles below. Switches S3 and S4 control the pull-up or pull-down resistor value attached to the MS_SEL and
SAOF pins of the CS8422, respectively. Each resistor value is sensed during the power-up sequence to
configure the device correctly. Consequently, for a modification to S3 or S4 to take affect, the CDB8422
should be reset by pressing push-button S5. For all switch positions, 0 = OPEN and 1 = CLOSED. See the
CS8422 data sheet for complete details of hardware mode behavior.
Due to a limited number of switches, the following CS8422 hardware mode configuration settings are not
changeable on the CDB8422: de-emphasis auto-detect is always enabled and the SRC MCLK is always the
PLL clock.
Also, some FPGA register settings are fixed in hardware mode. The MCLK sent to the SAO2 header J25 is
always the CS8422’s RMCK, the TDM subclocks at header J30 are always from SAO1, and the CS8406’s
V, U, C, TCBL, and AUDIO pins are always low.
Switch S3 controls the master/slave and clock ratio options for both serial output ports, see Table 3 for
switch configurations. For SDOUT1, when the serial port is set to master mode, the master clock ratio de-
termines what the output sample rate will be based on the MCLK selected for SDOUT1 (chosen by
position 6 on S7). For SDOUT2, the output sample rate is equal to the sample rate of the incoming receiver
data, and the master mode clock ratio determines the frequency of RMCK relative to the incoming receiver
sample rate.
MS_SEL[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
SDOUT1
Slave Mode
Master Mode, Fso = MCLK/128
Master Mode, Fso = MCLK/256
Master Mode, Fso = MCLK/512
Slave Mode
Master Mode, Fso = MCLK/128
Master Mode, Fso = MCLK/256
Master Mode, Fso = MCLK/512
Slave Mode
Master Mode, Fso = MCLK/128
Master Mode, Fso = MCLK/256
Master Mode, Fso = MCLK/512
Slave Mode
Master Mode, Fso = MCLK/128
Master Mode, Fso = MCLK/256
Master Mode, Fso = MCLK/512
Table 3. S3 Settings
SDOUT2
Slave Mode,
RMCK = 256*Fsi
Master Mode,
RMCK = 128*Fsi
Master Mode,
RMCK = 256*Fsi
Master Mode,
RMCK = 512*Fsi
Note:
Note:
DS692DB2
If SDOUT1 is set to slave mode, the SAO1 header J24 will be the master (not the CS8406) and the
CS8406’s OMCK/ILRCK ratio will be set to 256xFs.
If TDM Mode is selected for SDOUT1 by switch S4, then SDOUT1 cannot be set to “Master Mode,
Fso = MCLK/128”
25
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| CDB8427 | 功能描述:音频 IC 开发工具 Eval Bd 96kHz Dig. Audio Transcvr RoHS:否 制造商:Texas Instruments 产品:Evaluation Kits 类型:Audio Amplifiers 工具用于评估:TAS5614L 工作电源电压:12 V to 38 V |
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