参数资料
| 型号： | CDP68HC68T1MZ96 |
| 厂商： | Intersil |
| 文件页数： | 22/23页 |
| 文件大小： | 0K |
| 描述： | IC RTC RAM/SPI SERIAL 20-SOIC |
| 标准包装： | 1,000 |
| 类型： | 时钟/日历 |
| 特点： | 警报器，闰年，方波输出，监视计时器 |
| 存储容量： | 32B |
| 时间格式： | HH:MM:SS（12/24 小时） |
| 数据格式： | YY-MM-DD-dd |
| 接口： | SPI |
| 电源电压： | 3 V ~ 6 V |
| 电压 - 电源，电池： | 2.2 V ~ 6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 20-SOIC W |
| 包装： | 带卷 (TR) |
8
FN1547.8
October 29, 2007
Functional Description
The SPI real-time clock consists of a clock/calendar and a
32x8 RAM. Communications is established via the SPI
(Serial Peripheral Interface) bus. In addition to the
clock/calendar data from seconds to years, and system
flexibility provided by the 32-byte RAM, the clock features
computer handshaking with an interrupt output and a
separate squarewave clock output that can be one of seven
different frequencies. An alarm circuit is available that
compares the alarm latches with the seconds, minutes and
hours time counters and activates the interrupt output when
they are equal. The clock is specifically designed to aid in
power-down/power-up applications and offers several pins
to aid the designer of battery backup systems.
Mode Select
The voltage level that is present at the VSYS input pin at the
end of power-on-reset selects the device to be in the single
supply or battery backup mode.
Single-Supply Mode
If VSYS is a logic high when power-on-reset is completed, CLK
OUT, PSE and CPUR will be enabled and the device will be
completely operational. CPUR will be placed low if the logic
level at the VSYS pin goes low. If the output signals CLK OUT,
PSE and CPUR are disabled due to a power-down instruction,
VSYS brought to a logic low and then to a logic high will re-
enable these outputs. An example of the single-supply mode is
where only one supply is available and VDD, VBATT and VSYS
are tied together to the supply.
Battery Backup Mode
If VSYS is a logic low at the end of power-on-reset, CLK
OUT, PSE and CPUR will be disabled (CLK OUT, PSE and
CPUR low). This condition will be held until VSYS rises to a
threshold (about 1.0V) above VBATT. The outputs CLK OUT,
PSE and CPUR will then be enabled and the device will be
operational. If VSYS falls below a threshold above VBATT the
outputs CLK OUT, PSE and CPUR will be disabled. An
example of battery backup operation occurs if VSYS is tied to
VDD and VDD is not connected to a supply when a battery is
connected to the VBATT pin. (See "Functional Description",
The clock/calendar portion of this device consists of a long
string of counters that is toggled by a 1Hz input. The 1Hz
input is generated by a prescaler driven by an on-board
oscillator that utilizes one of four possible external crystals or
that can be driven by an external clock source. The 1Hz
trigger to the counters can also be supplied by a 50Hz or
60Hz input source that is connected to the LINE input pin.
The time counters offer seconds, minutes and hours data in
12 hour or 24 hour format. An AM/PM indicator is available
that once set, toggles every 12 hours. The calendar counters
consist of day (day of week), date (day of month), month and
years information. Data in the counters is in BCD format. The
hours counter utilizes BCD for hour data plus bits for 12/24 hour
and AM/PM. The seven time counters are accessed serially at
addresses 20H through 26H. See Table 1.
RAM
The real-time clock also has a static 32x8 RAM that is located
at addresses 00-1FH. Transmitting the address/control word
with Bit 5 low selects RAM access. Bits 0 through 4 select the
RAM location.
Alarm
The alarm is set by accessing the three alarm latches and
loading the required data. The alarm latches consist of
seconds, minutes and hours registers. When their outputs
equal the values in the seconds, minutes and hours time
counters, an interrupt is generated. The interrupt output will go
low if the alarm bit in the Interrupt Control Register is set high.
The alarm interrupt bit in the Status Register is set when the
interrupt occurs (see "Functional Description", INT Pin on
page 10). To preclude a false interrupt when loading the time
counters, the alarm interrupt bit should be set low in the
Interrupt Control Register. This procedure is not required when
the alarm time is set.
Watchdog Function (See Figure 6)
When Bit 7 in the Interrupt Control Register is set high, the
Clock’s CE (chip enable) pin must be toggled at a regular
interval without a serial data transfer. If the CE is not toggled,
the clock will supply a CPU reset pulse and Bit 6 in the Status
Register will be set. Typical service and reset times are listed in
Table 2.
Clock Out
The value in the three least significant bits of the Clock Control
Register selects one of seven possible output frequencies.
(See “Clock Control Register” on page 11). This squarewave
signal is available at the CLK OUT pin. When power-down
operation is initiated, the output is set low.
Control Registers and Status Registers
The operation of the Real-Time Clock is controlled by the Clock
Control and Interrupt Control Registers. Both registers are
Read-Write Registers. Another register, the Status Register, is
available to indicate the operating conditions. The Status
Register is a Read only Register.
Power Control
Power control is composed of two operations, Power Sense
and Power-Down/Power-Up. Two pins are involved in power
sensing, the LINE input pin and the INT output pin. Two
additional pins are utilized during power-down/power-up
operation. They are the PSE (Power Supply Enable) output
pin and VSYS input pin.
TABLE 2.
50Hz
60Hz
XTAL
MIN
MAX
MIN
MAX
MIN
MAX
Service Time
-
10ms
-
8.3ms
-
7.8ms
Reset Time
20
40ms
16.7
33.3ms
15.6
31.3ms
CDP68HC68T1
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相关代理商/技术参数 |
参数描述 |
|---|---|
| CDP68HC68T1W | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:CMOS Serial Real-Time Clock With RAM and Power Sense/Control |
| CDP68HC68T1W WAF | 制造商:Harris Corporation 功能描述: |
| CDP68HC68T2D | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Real-Time Clock |
| CDP68HC68T2E | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Real-Time Clock |
| CDP68HC68T2M | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Real-Time Clock |
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