参数资料
| 型号： | CDP68HC68T1MZ96 |
| 厂商： | Intersil |
| 文件页数： | 23/23页 |
| 文件大小： | 0K |
| 描述： | IC RTC RAM/SPI SERIAL 20-SOIC |
| 标准包装： | 1,000 |
| 类型： | 时钟/日历 |
| 特点： | 警报器，闰年，方波输出，监视计时器 |
| 存储容量： | 32B |
| 时间格式： | HH:MM:SS（12/24 小时） |
| 数据格式： | YY-MM-DD-dd |
| 接口： | SPI |
| 电源电压： | 3 V ~ 6 V |
| 电压 - 电源，电池： | 2.2 V ~ 6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 20-SOIC W |
| 包装： | 带卷 (TR) |
9
FN1547.8
October 29, 2007
Power Sensing (See Figure 3)
When Power Sensing is enabled (Bit 5 = 1 in Interrupt
Control Register), AC transitions are sensed at the LINE input
pin. Threshold detectors determine when transitions cease.
After a delay of 2.68ms to 4.64ms, plus the external input
circuit RC time constant, an interrupt is generated and a bit is
set in the Status Register. This bit can then be sampled to see
if system power has turned back on. See "Functional
Description", Line pin on page 10. The power-sense circuitry
operates by sensing the level of the voltage presented at the
line input pin. This voltage is centered around VDD and as
long as it is either plus or minus a threshold (about 1V) from
VDD a power-sense failure will not be indicated. With an AC
signal present, remaining in this VDD window longer than a
minimum of 2.68ms will activate the power-sense circuit. The
larger the amplitude of the AC signal, the less time it spends
in the VDD window, and the less likely a power failure will be
detected. A 60Hz, 10VP-P sinewave voltage is an applicable
signal to present at the LINE input pin to setup the power
sense function.
Power-Down (See Figure 4)
Power-down is a processor-directed operation. A bit is set in
the Interrupt Control Register to initiate operation. Three pins
are affected. The PSE (Power Supply Enable) output,
normally high, is placed low. The CLK OUT is placed low.
The CPUR output, connected to the processors reset input
is also placed low. In addition, the Serial Interface is
disabled.
Two conditions will terminate the Power-Down mode.
1. The first condition (see Figure 5) requires an interrupt.
The interrupt can be generated by the alarm circuit, the
programmable periodic interrupt signal, or the power
sense circuit.
FIGURE 3. POWER-SENSING FUNCTIONAL DIAGRAM
FIGURE 4. POWER-DOWN FUNCTIONAL DIAGRAM
FIGURE 5. POWER-UP FUNCTIONAL DIAGRAM (INITIATED
BY INTERRUPT SIGNAL
XTAL IN
XTAL OUT
LINE
VDD
REAL-TIME CLOCK
CDP68HC68T1
STATUS REGISTER
INT
CPU
CDP68HC05C16B
VDD
0V
I
VSYS
INTERRUPT
CONTROL
REGISTER
I
SERIAL
INTERFACE
CLK
OUT
CPUR
REAL-TIME CLOCK
CDP68HC68T1
PSE
OSC
RESET
CPU
CDP68HC05C4B
MISO
MOSI
FROM SYSTEM
POWER
TO SYSTEM
POWER CONTROL
POWER
SENSE
OR
ALARM
CIRCUIT
SERIAL
INTERFACE
PERIODIC
INTERRUPT
SIGNAL
POWER-UP
REAL-TIME CLOCK
CDP68HC68T1
PSE
CPUR
CLK
OUT
INT
MISO
MOSI
CDP68HC68T1
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相关代理商/技术参数 |
参数描述 |
|---|---|
| CDP68HC68T1W | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:CMOS Serial Real-Time Clock With RAM and Power Sense/Control |
| CDP68HC68T1W WAF | 制造商:Harris Corporation 功能描述: |
| CDP68HC68T2D | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Real-Time Clock |
| CDP68HC68T2E | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Real-Time Clock |
| CDP68HC68T2M | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Real-Time Clock |
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