参数资料
| 型号： | CDP68HC68T1MZ96 |
| 厂商： | Intersil |
| 文件页数： | 5/23页 |
| 文件大小： | 0K |
| 描述： | IC RTC RAM/SPI SERIAL 20-SOIC |
| 标准包装： | 1,000 |
| 类型： | 时钟/日历 |
| 特点： | 警报器，闰年，方波输出，监视计时器 |
| 存储容量： | 32B |
| 时间格式： | HH:MM:SS（12/24 小时） |
| 数据格式： | YY-MM-DD-dd |
| 接口： | SPI |
| 电源电压： | 3 V ~ 6 V |
| 电压 - 电源，电池： | 2.2 V ~ 6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 20-SOIC W |
| 包装： | 带卷 (TR) |
13
FN1547.8
October 29, 2007
Watchdog
If this bit is set high, the watchdog circuit has detected a
CPU failure.
Test Mode
When this bit is set high, the device is in the TEST MODE.
First-time Up
Power-on reset sets this bit high. This signifies that data in
the RAM and Clock is not valid and should be initialized.
Interrupt True
A high in this bit signifies that one of the three interrupts
(Power Sense, Alarm, and Clock) is valid.
Power-sense Interrupt
This bit set high signifies that the power-sense circuit has
generated an interrupt.
Alarm Interrupt
When the seconds, minutes and hours time and alarm
counter are equal, this bit will be set high. Status Register
must be read before loading Interrupt Control Register for
valid alarm indication after alarm activates.
Clock Interrupt
A periodic interrupt will set this bit high.
All bits are reset by a power-on reset except the “FIRST-
TIME UP” which is set. All bits except the power-sense bit
are reset after a read of this register.
Pin Signal Description
SCK (Serial Clock Input) (Note 11)
This input causes serial data to be latched from the MOSI
input and shifted out on the MISO output.
MOSI (Master Out/Slave In) (Note 11)
Data bytes are shifted in at this pin, most significant bit
(MSB) first.
MISO (Master In/Slave Out)
Data bytes are shifted out at this pin, most significant bit
(MSB) first.
CE (Chip Enable) (Note 12)
A positive chip-enable input. A low level at this input holds
the serial interface logic in a reset state, and disables the
output driver at the MISO pin.
NOTES:
11. These inputs will retain their previous state if the line driving them
goes into a High-Z state.
12. The CE input has as internal pull-down device, if the input is in a
low state before going to High Z, the input can be left in a High Z.
STATUS REGISTER (Read Only) - Address 30H
D7
D6
D5
D4
D3
D2
D1
D0
0
WATCHDOG
TEST
MODE
FIRST
TIME
UP
INTERRUPT
TRUE
POWER
SENSE
INTERRUPT
ALARM
INTERRUPT
CLOCK
INTERRUPT
TRUTH TABLE
MODE
SIGNAL
CE
SCK (Note 9)
MOSI
MISO
DISABLE
RESET
L
INPUT DISABLED
HIGH Z
WRITE
H
CPOL = 1
CPOL = 0
DATA BIT LATCH
HIGH Z
READ
H
CPOL = 1
CPOL = 0
X
NEXT DATA BIT
SHIFTED OUT
(Note 10)
NOTES:
9. When interfacing to CDP68HC05 microcontrollers, serial clock phase bit, CPHA, must be set = 1 in the microcomputer’s Control Register.
10. MISO remains at a high Z until 8-bits of data are ready to be shifted out during a READ. It remains at a high Z during the entire WRITE cycle.
CDP68HC68T1
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相关代理商/技术参数 |
参数描述 |
|---|---|
| CDP68HC68T1W | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:CMOS Serial Real-Time Clock With RAM and Power Sense/Control |
| CDP68HC68T1W WAF | 制造商:Harris Corporation 功能描述: |
| CDP68HC68T2D | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Real-Time Clock |
| CDP68HC68T2E | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Real-Time Clock |
| CDP68HC68T2M | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Real-Time Clock |
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