参数资料
型号: CH7303
厂商: Electronic Theatre Controls, Inc.
英文描述: Chrontel CH7303 HDTV / DVI Encoder
中文描述: 昆泰CH7303的HDTV / DVI译码器
文件页数: 12/15页
文件大小: 330K
代理商: CH7303
CHRONTEL
CH7303
12
209-0000-031
Rev. 0.4,
8/26/2002
Note :
V
DATA
- refers to all digital data (D[14:0]), clock (XCLK, XCLK*), sync (H, V) and DE inputs.
V
MISC
- refers to GPIOx, RESET*, AS and
HPDET inputs and GPIOx, VSYNC and HSYNC outputs.
3.5
AC Specifications
Symbol
Description
Test Condition
Min
Typ
Max
Unit
f
XCLK
Input (XCLK) frequency
25
165
MHz
t
PIXEL
Pixel time period
6.06
40
ns
DC
XCLK
Input (XCLK) Duty Cycle
T
S
+ T
H
< 1.2ns
30
70
%
t
XJIT
XCLK clock jitter tolerance
f
XCLK
= 75MHz
2
ns
t
DVIR
DVI Output Rise Time
(20% - 80%)
f
XCLK
= 165MHz
75
242
ps
t
DVIF
DVI Output Fall Time
(20% - 80%)
f
XCLK
= 165MHz
75
242
ps
t
SKDIFF
DVI Output intra-pair skew
f
XCLK
= 165MHz
90
ps
t
SKCC
DVI Output inter-pair skew
f
XCLK
= 165MHz
1.2
ns
t
DVIJIT
DVI Output Clock Jitter
f
XCLK
= 165MHz
150
ps
T
S
Setup Time: D[11:0], H, V and
DE to XCLK, XCLK*
XCLK = XCLK* to
D[11:0], H, V, DE =
Vref
TBD
ns
T
H
Hold Time: D[11:0], H, V and
DE to XCLK, XCLK*
D[11:0], H, V, DE =
Vref to XCLK =
XCLK*
TBD
ns
t
STEP
De-skew time increment
50
80
ps
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