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参数资料
| 型号： | CH7303 |
| 厂商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Chrontel CH7303 HDTV / DVI Encoder |
| 中文描述： | 昆泰CH7303的HDTV / DVI译码器 |
| 文件页数： | 6/15页 |
| 文件大小： | 330K |
| 代理商： | CH7303 |
CHRONTEL
CH7303
6
209-0000-031
Rev. 0.4,
8/26/2002
Table 4: EDTV Bypass
Active
Resolution
720x480
720x483
720x480
720x483
720x576
2.1.2
In RGB Bypass mode, data, sync and clock signals are input to the CH7303 from a graphics device, and bypassed
directly to the D/A converters to implement a second CRT DAC function. External sync signals must be supplied from
the graphics device. These sync signals are buffered internally, and can be output to drive the CRT. The input data
format must be RGB in this operating mode. Input data is 2X multiplexed, and the XCLK clock signal can be 1X or 2X
times the pixel rate. The CH7303 can support a pixel rate of 165MHz. This operating mode uses all 8 bits of the DAC’s
10-bit range, and provides a nominal signal swing of 0.661V (or 0.7V depending on DAC Gain setting in control
registers) when driving a 75
doubly terminated load. No scaling, scan conversion or flicker filtering is applied in
Bypass modes.
2.2
DVI Output
2.2.1
DVI Transmitter
In DVI Output mode, multiplexed input data, sync and clock signals are input to the CH7303 from the graphics
controller’s digital output port. Data will be 2X multiplexed, and the clock inputs can be 1X or 2X times the pixel rate.
Some examples of modes supported are shown in the table. For the table below, clock frequencies for given modes were
taken from VESA DISPLAY MONITOR TIMING SPECIFICATIONS if they were detailed there, not VESA TIMING
DEFINITION FOR FLAT PANEL MONITORS. The device is not dependent upon this set of timing specifications.
Any values of pixels/line, lines/frame and clock rate are acceptable, as long as the pixel rate remains below 165MHz.
The input format can be any RGB format or YCrCb (see Input Data Formats section).
Table 9: DVI Output
Graphics
Resolution
Ratio
Ratio
(Hz)
Total
Resolution
858x525
858x525
856x525
856x525
864x625
Scan Type
Pixel Clock
(MHz)
27.0
27.027
26.937
26.964
27.0
Frame Rate
(Hz)
60/1.001
60
60/1.001
60
50
Standard
Non-Interlaced
Non-Interlaced
Non-Interlaced
Non-Interlaced
Non-interlaced
EIA-770.2-A
SMPTE 293M
ITU-R BT.1358
RGB Bypass
Active Aspect
Pixel Aspect
Refresh Rate
XCLK
Frequency
(MHz)
<35.5
<31.5
<36
27
27
<57
<95
<67
DVI
Frequency
(MHz)
<355
<315
<360
270
270
<570
<950
<670
720x400
640x400
640x480
720x480
720x576
800x600
1024x768
1280x720
4:3
8:5
4:3
4:3
4:3
4:3
4:3
16:9
1.35:1.00
1:1
1:1
9:8
15:12
1:1
1:1
1:1
<85
<85
<85
59.94
50
<85
<85
<60
2.3
2.3.1
Two distinct methods of transferring data to the CH7303 are described. They are:
Multiplexed data, clock input at 1X the pixel rate
Multiplexed data, clock input at 2X the pixel rate
For the multiplexed data, clock at 1X pixel rate, the data applied to the CH7303 is latched with both edges of the clock
(also referred to as dual edge transfer mode or DDR). For the multiplexed data, clock at 2X pixel rate the data applied to
the CH7303 is latched with one edge of the clock (also known as single edge transfer mode or SDR). The polarity of the
pixel clock can be reversed under serial port control. In single edge transfer modes, the clock edge used to latch data is
programmable. In dual edge transfer modes, the clock edge used to latch the first half of each pixel is programmable.
Input Interface
Overview
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