参数资料
| 型号： | CS5165AGDW16 |
| 厂商： | ON Semiconductor |
| 文件页数： | 12/18页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR BUCK SYNC 5BIT 16-SOIC |
| 产品变化通告： | Product Obsolescence 11/Feb/2009 Product Obsolescence 30/Dec/2003 |
| 标准包装： | 47 |
| 应用： | 控制器，Intel Pentium? II |
| 输入电压： | 8 V ~ 14 V |
| 输出数： | 2 |
| 输出电压： | 1.34 V ~ 2.09 V，2.14 V ~ 3.54 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 16-SOIC W |
| 包装： | 管件 |
CS5165A
remain in this state until the overvoltage condition ceases or the
input voltage is pulled low. The bottom FET and board trace
V CORE
must be properly designed to implement the OVP function.If
15 k
R1
a dedicated OVP output is required, it can be implemented
using the circuit in Figure 22. In this figure the OVP signal will
go high (overvoltage condition), if the output voltage (V CORE )
exceeds 20% of the voltage set by the particular DAC code and
provided that PWRGD is low. It is also required that the
+5.0 V
5.0 k
56 k
R2
Q3
2N3906
OVP
overvoltage condition be present for at least the PWRGD delay
time for the OVP signal to be activated. The resistor values
shown in Figure 22 are for V DAC = +2.8 V (DAC = 10111).
CS5165A
+5.0 V
10 k
10 k
20 k
Q2
2N3904
10 K
The V OVP (overvoltage trip?point) can be set using the
following equation:
PWRGD
Q1
2N3906
VOVP + VBEQ3 1 ) R2
R1
M 10.0 m s
Trace 4? 5.0 V from PC Power Supply (5.0 V/div.)
Trace 1? Regulator Output Voltage (1.0 V/div.)
Trace 2? Inductor Switching Node 5.0 V/div.)
Figure 20. OVP Response to an Input?to?Output
Short Circuit by Immediately Providing 0% Duty
Cycle, Crow?Barring the Input Voltage to Ground
M 5.00 ms
Trace 4? 5.0 V from PC Power Supply (2.0 V/div.)
Trace 1? Regulator Output Voltage (1.0 V/div.)
Figure 21. OVP Response to an Input?to?Output Short
Circuit by Pulling the Input Voltage to Ground
Figure 22. Circuit To Implement A Dedicated OVP
Output Using The CS5165A
Output Enable Circuit
The Enable pin (pin 8) is used to enable or disable the
regulator output voltage, and is consistent with TTL DC
specifications. It is internally pulled?up. If pulled low (below
0.8 V), the output voltage is disabled. At the same time the
Power Good and Soft?Start pins are pulled low, so that when
normal operation resumes power?up of the CS5165A goes
through the Soft?Start sequence. Upon pulling the Enable pin
low, the internal IC bias is completely shut off, resulting in
total shutdown of the Controller IC.
Power Good Circuit
The Power Good pin (pin 13) is an open?collector signal
consistent with TTL DC specifications. It is externally
pulled?up, and is pulled low (below 0.3 V) when the regulator
output voltage typically exceeds ± 8.5% of the nominal output
voltage. Maximum output voltage deviation before Power
Good is pulled low is ± 12%.
Trace 2? PWRGD (2.0 V/div.)
Trace 4? V OUT (1.0 V/div.)
Figure 23. PWRGD Signal Becomes Logic High as
V OUT Enters ?8.5% of Lower PWRGD Threshold,
V OUT = +2.84 V (DAC = 10111)
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相关代理商/技术参数 |
参数描述 |
|---|---|
| CS5165AGDW16G | 功能描述:DC/DC 开关控制器 5-Bit Synchronous Dual N-Channel Buck RoHS:否 制造商:Texas Instruments 输入电压:6 V to 100 V 开关频率: 输出电压:1.215 V to 80 V 输出电流:3.5 A 输出端数量:1 最大工作温度:+ 125 C 安装风格: 封装 / 箱体:CPAK |
| CS5165AGDWR16 | 功能描述:DC/DC 开关控制器 5-Bit Synchronous RoHS:否 制造商:Texas Instruments 输入电压:6 V to 100 V 开关频率: 输出电压:1.215 V to 80 V 输出电流:3.5 A 输出端数量:1 最大工作温度:+ 125 C 安装风格: 封装 / 箱体:CPAK |
| CS5165AGDWR16G | 功能描述:DC/DC 开关控制器 ANA BUCK SYNC 5BIT CNTRLR RoHS:否 制造商:Texas Instruments 输入电压:6 V to 100 V 开关频率: 输出电压:1.215 V to 80 V 输出电流:3.5 A 输出端数量:1 最大工作温度:+ 125 C 安装风格: 封装 / 箱体:CPAK |
| CS-5165DW16 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Voltage-Mode SMPS Controller |
| CS-5165DWR16 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Voltage-Mode SMPS Controller |
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