参数资料
型号: CS5165AGDW16
厂商: ON Semiconductor
文件页数: 17/18页
文件大小: 0K
描述: IC CTRLR BUCK SYNC 5BIT 16-SOIC
产品变化通告: Product Obsolescence 11/Feb/2009
Product Obsolescence 30/Dec/2003
标准包装: 47
应用: 控制器,Intel Pentium? II
输入电压: 8 V ~ 14 V
输出数: 2
输出电压: 1.34 V ~ 2.09 V,2.14 V ~ 3.54 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 16-SOIC(0.295",7.50mm 宽)
供应商设备封装: 16-SOIC W
包装: 管件
CS5165A
1. Rapid changes in voltage across parasitic capacitors
and abrupt changes in current in parasitic inductors
are major concerns for a good layout.
2. Keep high currents out of logic grounds.
3. Avoid ground loops as they pick up noise. Use star or
single point grounding. The source of the lower
(synchronous FET) is an ideal point where the input
and output GND planes can be connected.
4. For double?sided PCBs a single large ground plane is
not recommended, since there is little control of
where currents flow and the large surface area can act
as an antenna.
5. Even though double sided PCBs are usually sufficient
for a good layout, four?layer PCBs are the optimum
approach to reducing susceptibility to noise. Use the
two internal layers as the +5.0 V and GND planes, and
the top and bottom layers for the vias.
6. Keep the inductor switching node small by placing
the output inductor, switching and synchronous FETs
close together.
5.0 V
MBRS120
7. The FET gate traces to the IC must be as short,
straight, and wide as possible. Ideally, the IC has to be
placed right next to the FETs.
8. Use fewer, but larger output capacitors, keep the
capacitors clustered, and use multiple layer traces
with heavy copper to keep the parasitic resistance
low.
9. Place the switching FET as close to the +5.0 V input
capacitors as possible.
10. Place the output capacitors as close to the load as
possible.
11. Place the V FB filter resistor in series with theV FB pin
(pin 16) right at the pin.
12. Place the V FB filter capacitor right at the V FB pin
(pin 16).
13. The “Droop” Resistor (embedded PCB trace) has to
be wide enough to carry the full load current.
14. Place the V CC bypass capacitor as close as possible to
the V CC pin.
1.0 m F
MBRS120
MBRS120
V CC
1.0 m F
1200 m F/10 V × 3
Droop Resistor
V GATE(H)
V ID3
V ID0
V ID1 CS5165A
V ID2
V GATE(L)
V ID4 PGND
Si4410DY
Si9410DY
1.2 m H
(Embedded PCB trace)
6.0 m W
+
1200 m F/10 V × 5
V CC
V SS
C OFF
330 pF
0.1 m F
ENABLE
PWRGD
SS
V FB
COMP LGND
0.1 m F
1000 pF
3.3 k
ENABLE
PWRGD
PENTIUM II
SYSTEM
V ID4
V ID3
V ID2
V ID1
V ID0
Figure 28. Additional Application Diagram, +5.0 V to +2.8 V @ 14.2 A for 300 MHz Pentium II
http://onsemi.com
17
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