参数资料
| 型号： | CS5165AGDW16 |
| 厂商： | ON Semiconductor |
| 文件页数： | 3/18页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR BUCK SYNC 5BIT 16-SOIC |
| 产品变化通告： | Product Obsolescence 11/Feb/2009 Product Obsolescence 30/Dec/2003 |
| 标准包装： | 47 |
| 应用： | 控制器，Intel Pentium? II |
| 输入电压： | 8 V ~ 14 V |
| 输出数： | 2 |
| 输出电压： | 1.34 V ~ 2.09 V，2.14 V ~ 3.54 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 16-SOIC W |
| 包装： | 管件 |
CS5165A
ELECTRICAL CHARACTERISTICS (0 ° C < T A < +70 ° C; 0 ° C < T J < +125 ° C; 8.0 V < V CC < 14 V; 2.8 DAC Code:
(V ID4 = V ID2 = V ID1 = V ID0 = 1; V ID3 = 0) ; C GATE(H) and C GATE(L) = 3.3 nF; C OFF = 330 pF; C SS = 0.1 m F, unless otherwise specified.)
Characteristic
Test Conditions
Min
Typ
Max
Unit
V CC Supply Current
Operating
1.0 V < V FB < V DAC (max on?time)
?
12
20
mA
No Loads on GATE(H) and GATE(L)
Sleep Mode
ENABLE = 0 V
?
300
600
m A
V CC Monitor
Start Threshold
Stop Threshold
Hysteresis
GATE(H) switching
GATE(H) not switching
Start?Stop
3.75
3.65
?
3.95
3.87
80
4.15
4.05
?
V
V
mV
Error Amplifier
V FB Bias Current
COMP Source Current
COMP CLAMP Voltage
COMP Clamp Current
COMP Sink Current
Open Loop Gain
Unity Gain Bandwidth
PSRR @ 1.0 kHz
V FB = 0 V
COMP = 1.2 V to 3.6 V; V FB = 2.7 V
V FB = 2.7 V, Adjust COMP voltage for Comp current = 50 m A
COMP = 0 V
V COMP = 1.2 V; V FB = 3.0 V; V SS > 2.5 V
(Note 2)
(Note 2)
(Note 2)
?
15
0.85
0.4
180
50
0.5
60
0.1
30
1.0
1.0
400
60
2.0
85
1.0
60
1.15
1.6
800
?
?
?
m A
m A
V
mA
m A
dB
MHz
dB
GATE(H) and GATE(L)
High Voltage at 100 mA
Low Voltage at 100 mA
Rise Time
Fall Time
GATE(H) to GATE(L) Delay
GATE(L) to GATE(H) Delay
GATE pulldown
Measure V CC ? GATE
Measure GATE
1.6 V < GATE < (V CC ? 2.5 V)
(V CC ? 2.5 V) > GATE > 1.6 V
GATE(H) < 2.0 V; GATE(L) > 2.0 V
GATE(L) < 2.0 V; GATE(H) > 2.0 V
Resistor to PGND, (Note 2)
?
?
?
?
30
30
20
1.2
1.0
40
40
65
65
50
2.0
1.5
80
80
100
100
115
V
V
ns
ns
ns
ns
k W
Fault Protection
SS Charge Time
SS Pulse Period
SS Duty Cycle
SS COMP Clamp Voltage
V FB Low Comparator
V FB = 0 V
V FB = 0 V
(Charge Time/Period) × 100
V FB = 2.7 V; V SS = 0 V
Increase V FB till no SS pulsing and normal Off?time
1.6
25
1.0
0.50
0.9
3.3
100
3.3
0.95
1.0
5.0
200
6.0
1.10
1.1
ms
ms
%
V
V
PWM Comparator
Transient Response
V FB = 1.2 to 5.0 V. 500 ns after GATE(H)
?
130
180
ns
(after Blanking time) to GATE(H) = (V CC ?1.0 V) to 1.0 V
Minimum Pulse Width
Drive V FB. 1.2 to 5.0 V upon GATE(H) rising edge
50
150
250
ns
(Blanking Time)
C OFF
(> V CC ? 1.0 V), measure GATE(H) pulse width
Normal Off?Time
Extended Off?Time
V FB = 2.7 V
V SS = V FB = 0 V
1.0
5.0
1.6
8.0
2.3
12.0
m s
m s
Time?Out Timer
Time?Out Time
Fault Duty Cycle
V FB = 2.7 V, Measure GATE(H) Pulse Width
V FB = 0V
10
30
30
50
50
70
m s
%
Enable Input
ENABLE Threshold
Shutdown delay (Note 3)
GATE(H) Switching
ENABLE?to?GATE(H) < 2.0 V
0.8
?
1.15
3.0
1.30
?
V
m s
2. Guaranteed by design, not 100% tested in production.
http://onsemi.com
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