参数资料
型号: CS5165AGDW16
厂商: ON Semiconductor
文件页数: 6/18页
文件大小: 0K
描述: IC CTRLR BUCK SYNC 5BIT 16-SOIC
产品变化通告: Product Obsolescence 11/Feb/2009
Product Obsolescence 30/Dec/2003
标准包装: 47
应用: 控制器,Intel Pentium? II
输入电压: 8 V ~ 14 V
输出数: 2
输出电压: 1.34 V ~ 2.09 V,2.14 V ~ 3.54 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 16-SOIC(0.295",7.50mm 宽)
供应商设备封装: 16-SOIC W
包装: 管件
CS5165A
PACKAGE PIN DESCRIPTION
PACKAGE PIN #
SOIC?16
1, 2, 3, 4, 6
5
7
8
9
10
11
12
13
14
15
16
PIN SYMBOL
V ID0 ?V ID4
SS
C OFF
ENABLE
V CC
GATE(H)
PGND
GATE(L)
PWRGD
LGND
COMP
V FB
FUNCTION
Voltage ID DAC input pins. These pins are internally pulled up to 5.0 V if left open. V ID4 selects
the DAC range. When V ID4 is high (logic one), the Error Amp reference range is 2.14 V to 3.45 V
with 100 mV increments. When V ID4 is low (logic zero), the Error Amp reference voltage 1.34 V
to 2.09 V with 50 mV increments.
Soft?Start Pin. A capacitor from this pin to LGND sets the Soft?Start and fault timing.
Off?Time Capacitor Pin. A capacitor from this pin to LGND sets both the normal and extended off
time.
Output Enable Input. This pin is internally pulled up to 1.8 V. A logic Low (< 0.8) on this pin
disables operation and places the CS5165A into a low current sleep mode.
Input Power Supply Pin.
High Side Switch FET driver pin.
High current ground for the GATE(H) and GATE(L) pins.
Low Side Synchronous FET driver pin.
Power Good Output. Open collector output drives low when V FB is out of regulation. Active when
ENABLE input is low.
Reference ground. All control circuits are referenced to this pin.
Error Amp output. PWM Comparator reference input. A capacitor to LGND provides Error Amp
compensation.
Error Amp, PWM Comparator, and Low V FB Comparator feedback input.
ENABLE
V CC
20 k
7.0 m A
?
Circuit Bias
V CC Monitor
?
+
3.95 V
3.87V
V CC
+
1.25 V
Enable
Comparator
5.0 V
?
SS Low
Comparator
R
Q
FAULT
V GATE(H)
SS
60 m A
2.0 m A
0.7 V
+
+
?
SS High
Comparator
S Q
FAULT
Latch
FAULT
PGND
V CC
V CC1
V GATE(L)
2.5 V
COMP
V ID0
Error Amplifier
PGND
Blanking
V ID1
V ID2
V ID3
V ID4
?8.5%
5 BIT
DAC
+8.5%
+ ?
?
+
+
?
?
+
PWM
Comparator
PWM COMP
Maximum
On?Time
Timeout
Normal
Off?Time
Timeout
R Q
S Q
PWM
Latch
GATE(H) = ON
GATE(H) = OFF
C OFF
One Shot
Extended
Off?Time
Timeout
Off?Time
Timeout
R
S
Q
C OFF
PWRGD
65 m s
Delay
V FB
1.0 V
?
+
V FB Low
Comparator
Time?Out
Timer
(30 m s)
Edge Triggered
LGND
Figure 2. Block Diagram
http://onsemi.com
6
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