参数资料
型号: CS5376A-IQZ
厂商: Cirrus Logic Inc
文件页数: 14/49页
文件大小: 0K
描述: IC FILTER DGTL MULTI-CH 64-TQFP
标准包装: 160
滤波器类型: 数字
滤波器数: 4
滤波器阶数: 2nd
电源电压: 3 V ~ 5 V
安装类型: 表面贴装
封装/外壳: 64-LQFP
供应商设备封装: 64-TQFP(10x10)
包装: 管件
配用: 598-1778-ND - EVALUATION BOARD FOR CS5376
2008 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FUSB2805 Rev. 1.0.3
21
F
USB2
8
0
5
USB2
.0
High
-S
pee
d
OTG
Tra
nsc
e
iv
e
rw
ith
UL
P
I
Inter
fac
e
Receive Command (RXCMD)
The FUSB2805, after asserting DIR, uses the receive
command (RXCMD) byte to update the link on line
state, USB receive, disconnect, and OTG information
via the ULPI data bus.
The
FUSB2805
automatically
sends
an
RXCMD
whenever there is a change in any of the RXCMD data
fields. The link must be able to accept an RXCMD at
any time; including single or multiple (back-to-back)
RXCMDs and, at any time during USB receive packets,
when NXT is LOW.
Table 9.
RXCMD Data Byte Format
DATA[7:0]
Status Name
Description
[1:0]
LINESTATE
Line State Signals:
D[0]: LINESTATE0
D[1]: LINESTATE1
LINESTATE[1:0] reflects the current status of DP and DM and is a function of
various register settings and whether the device is a host or peripheral. The detailed
encoding, and descriptions thereof, is shown in Table 10 and Table 11.
[3:2]
VBUS State
Encoded VBUS Voltage State: This encoding is used for over-current detection,
session start, and session request (SRP). The Sess_End and Sess_VLD indicators
are signals from the internal FUSB2805 VBUS comparators. These encoded VBUS
states are:
Value
VBUS Voltage
Sess_End
Sess_VLD
A_VBUS_VLD
00b
VBUS < VB_Sess_End
1
0
01b
VB_Sess_End ≤ VBUS <
VA_Sess_Vld
0
10b
VA_Sess_Vld ≤ VBUS <
VA_VBUS_Vld
X
1
0
11b
VBUS ≥ VA_VBUS_VLD
X
1
[5:4]
RxEvent
RxEvent Encoding: This encoding field of RXCMD is used to inform the link of
information packets received on the USB bus. These events are:
Value
RxError
RxActive
HostDisconnect
00b
0
01b
0
1
0
10b
X
1
11b
1
0
[6]
ID
This bit reflects the state of the ID pin. It is valid 50ms after ID_PULLUP is set to 1b.
[7]
ALT_INT
Default is not to use this alternate interrupt bit. The link, optionally, can enable the
BVALID_RISE and/or BVALID_FALL bits in the PWR_CNTRL register.
Corresponding changes in BVALID cause an RXCMD to be sent to the link with this
ALT_INT bit asserted.
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