参数资料
| 型号： | CS5376A-IQZ |
| 厂商： | Cirrus Logic Inc |
| 文件页数： | 23/49页 |
| 文件大小： | 0K |
| 描述： | IC FILTER DGTL MULTI-CH 64-TQFP |
| 标准包装： | 160 |
| 滤波器类型： | 数字 |
| 滤波器数： | 4 |
| 滤波器阶数： | 2nd |
| 电源电压： | 3 V ~ 5 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-LQFP |
| 供应商设备封装： | 64-TQFP（10x10） |
| 包装： | 管件 |
| 配用： | 598-1778-ND - EVALUATION BOARD FOR CS5376 |
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2008 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FUSB2805 Rev. 1.0.3
3
F
USB2
8
0
5
—
USB2
.0
High
-S
pee
d
OTG
Tra
nsc
e
iv
e
rw
ith
UL
P
I
Inter
fac
e
Pin Definitions
Symbol
Type
Description
Chip Select_N
I
Active LOW. HIGH
– ULPI pin three-stated; LOW – ULPI operates normally. TTL
compatible; CMOS input with hysteresis.
RREF
AI/O
Resistor reference. Connect through 12 k
1% to GND.
DM
AI/O
USB D- pin. USB mode: data minus (D-) pin of the USB cable.
DP
AI/O
USB D+ pin. USB mode: data plus (D+) pin of the USB cable.
FAULT
I
FAULT is used to signal a VBUS over-current/over-voltage condition from an external
SMPS or power management IC. The link must enable this function via the
ExternalVbusFault register bit and the polarity must be set via the
ExternalVbusActiveLow register bit.
ID
I
Identification (ID) pin of the micro-USB cable. TTL; if not used, connect to 3V3.
VCC
P
Input supply voltage or battery source.
PSW
O
Controls an external, active HIGH,
VBUS power switch/charge pump and/or an SMPS
charger IC. An external 100 k
pull-down resistor is required. Open source, slew-rate-
controlled output; this pin is referenced to VCC3V3.
VBUS
AI/O
Should be connected to the VBUS pin of the USB cable. Leave open circuit if not used.
An internal 90 k
±11% pull-down resistor is present on this pin.
VCC3V3
P
3.3 V regulator output requiring capacitors. Internally powers OTG, analog core, and
ATX.
CLKIN
I
Clock input; frequency depends on the CFG1 pin. This is a digital input buffer, not
analog for a crystal.
I.C.
I/O
Internally connected; float pin.
TEST
I/O
Internally connected; float pin.
CFG1
I
Configures the clock frequency; 0: input is 19.2 MHz. 1: input is 26 MHz.
VDD1V2
P
1.2 V regulator output requiring capacitors. Internally powers the digital core and
analog core.
VIO
P
Input I/O supply rail; 0.1 F capacitor connected to power input.
Reset_N
I
Connect to VIO when not used. Resets the transceiver; active LOW.
GND
P
Connect to ground.
DIR
O
ULPI direction output signal.
STP
I
ULPI stop input signal; CMOS input.
NXT
O
ULPI next output signal.
D7
I/O
ULPI data pin 7; three-state output.
D6
I/O
ULPI data pin 6; three-state output.
D5
I/O
ULPI data pin 5; three-state output.
D4
I/O
ULPI data pin 4; three-state output.
D3
I/O
ULPI data pin 3; three-state output.
D2
I/O
ULPI data pin 2; three-state output.
D1
I/O
ULPI data pin 1; three-state output.
D0
I/O
ULPI data pin 0; three-state output.
CLOCK
O
60 MHz clock output when digital 19.2 MHz (or 26 MHz) clock is applied; Push-pull
output.
Notes:
1.
I=input; O=output; I/O=digital input/output; OD=open-drain output; AI/O=analog input/output; P=power or ground.
2.
Per USB2.0, below a supply of 2.97 V, USB full-speed and low-speed transactions are not guaranteed; although
some devices may continue to function with the FUSB2805 at the lower supply rail.
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