参数资料
型号: CS5460A-BSZ
厂商: Cirrus Logic Inc
文件页数: 5/54页
文件大小: 0K
描述: IC ENERGY METERING 1PHASE 24SSOP
标准包装: 59
输入阻抗: 30 千欧
测量误差: 0.1%
电压 - 高输入/输出: 0.8V
电压 - 低输入/输出: 0.2V
电流 - 电源: 2.9mA
电源电压: 4.75 V ~ 5.25 V
测量仪表类型: 单相
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 24-SSOP(0.209",5.30mm 宽)
供应商设备封装: 24-SSOP
包装: 管件
产品目录页面: 754 (CN2011-ZH PDF)
配用: CDB5460AU-ND - EVALUATION BOARD FOR CS5460A
其它名称: 598-1094-5
CS5460A
1. CHARACTERISTICS & SPECIFICATIONS
ANALOG CHARACTERISTICS
(T A = -40 °C to +85 °C; VA+ = VD+ = +5 V ±10%; VREFIN = +2.5 V; VA- = AGND = 0 V; MCLK = 4.096 MHz,
K = 1; N = 4000 ==> OWR = 4000 Sps.)(See Notes 1, 2, 3, 4, and 5.)
Parameter
Symbol
Min
Typ
Max
Unit
Accuracy (Both Channels)
Common Mode Rejection
Offset Drift (Without the High Pass Filter)
(DC, 50, 60 Hz)
CMRR
80
-
-
5
-
-
dB
nV/°C
Analog Inputs (Current Channel)
Maximum Differential Input Voltage Range
(Gain = 10)
I IN
-
-
500
mV P-P
{(V IIN+ ) - (V IIN- )}
Total Harmonic Distortion
Common Mode + Signal on IIN+ or IIN-
(Gain = 50)
(Gain = 10 or 50)
THD I
-
80
-0.25
-
-
-
100
-
VA+
mV P-P
dB
V
Crosstalk with Voltage Channel at Full Scale
(50, 60 Hz)
-
-
-115
dB
Input Capacitance
Effective Input Impedance
Noise (Referred to Input)
(Gain = 10)
(Gain = 50)
(Note 6)
(Gain = 10)
(Gain = 50)
(Gain = 10)
(Gain = 50)
C in
Z inI
Z inI
-
-
-
-
-
-
25
25
30
30
-
-
-
-
-
-
20
4
pF
pF
k ?
k ?
μV rms
μV rms
Accuracy (Current Channel)
Bipolar Offset Error
Full-Scale Error
(Note 1)
(Note 1)
VOS I
FSE I
-
-
±0.001
±0.001
-
-
%F.S.
%F.S.
Analog Inputs (Voltage Channel)
Maximum Differential Input Voltage Range
Total Harmonic Distortion
Common Mode + Signal on VIN+ or VIN-
{(V VIN+ ) - (V VIN- )}
V IN
THD V
-
62
VA-
-
-
-
500
-
VA+
mV P-P
dB
V
Crosstalk with Current Channel at Full Scale
Input Capacitance
(50, 60 Hz)
C inV
-
-
-
0.2
-70
-
dB
pF
Effective Input Impedance
Noise (Referred to Input)
(Note 6)
Z inV
-
-
5
-
-
250
M ?
μV rms
Accuracy (Voltage Channel)
Bipolar Offset Error
Full-Scale Error
(Note 1)
(Note 1)
VOS V
FSE V
-
-
±0.01
±0.01
-
-
%F.S.
%F.S.
Notes: 1. Bipolar Offset Errors and Full-Scale Gain Errors for the current and voltage channels refer to the respective Irms
Register and Vrms Register output, when the device is operating in ‘continuous computation cycles’ data acquisition
mode, after offset/gain system calibration sequences have been executed. These specs do not apply to the error
of the Instantaneous Current/Voltage Register output.
2.
3.
4.
5.
6.
DS487F5
Specifications guaranteed by design, characterization, and/or test.
Analog signals are relative to VA- and digital signals to DGND unless otherwise noted.
In requiring VA+ = VD+ =5 V ±10%, note that it is allowable for VA+, VD+ to differ by as much as ±200 mV, as long
as VA+ > VD+.
Note that “Sps” is an abbreviation for units of “samples per second”.
Effective Input Impedance (Zin) is determined by clock frequency (DCLK) and Input Capacitance (IC).
Zin = 1/(IC*DCLK/4). Note that DCLK = MCLK / K.
5
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