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参数资料
| 型号： | CS5460A-BSZ |
| 厂商： | Cirrus Logic Inc |
| 文件页数： | 50/54页 |
| 文件大小： | 0K |
| 描述： | IC ENERGY METERING 1PHASE 24SSOP |
| 标准包装： | 59 |
| 输入阻抗： | 30 千欧 |
| 测量误差： | 0.1% |
| 电压 - 高输入/输出： | 0.8V |
| 电压 - 低输入/输出： | 0.2V |
| 电流 - 电源： | 2.9mA |
| 电源电压： | 4.75 V ~ 5.25 V |
| 测量仪表类型： | 单相 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-SSOP（0.209"，5.30mm 宽） |
| 供应商设备封装： | 24-SSOP |
| 包装： | 管件 |
| 产品目录页面： | 754 (CN2011-ZH PDF) |
| 配用： | CDB5460AU-ND - EVALUATION BOARD FOR CS5460A |
| 其它名称： | 598-1094-5 |
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CS5460A
CRDY
EDIR
EOUT
DRDY
Conversion Ready. Indicates a new conversion is ready. This will occur at the output word rate,
which is usually 4 kHz.
Set whenever the EOUT bit asserted (see below) if the accumulated energy is negative.
Indicates that enough positive/negative energy has been reached within the internal EOUT En-
ergy Accumulation Register (not accessible to user) to mandate the generation of one or more
pulses on the EOUT pin (if enabled, see Configuration Register ). The energy flow may indicate
negative energy or positive energy. (The sign is determined by the EDIR bit, described above).
This EOUT bit is cleared automatically when the energy rate drops below the level that produc-
es a 4 kHz EOUT pin rate. The bit can also be cleared by writing to the Status Register. This
status bit is set with a maximum frequency of 4 kHz (when MCLK/K is 4.096 MHz). When
MCLK/K is not equal to 4.096 MHz, the user should scale the pulse-rate by a factor of
4.096 MHz / (MCLK/K) to get the actual pulse-rate.
Data Ready. When running in ’single computation cycle’ or ’continuous computation cycles’
data acquisition modes, this bit will indicate the end of computation cycles. When running cali-
brations, this bit indicates that the calibration sequence has completed, and the results have
been stored in the offset or gain registers.
5.12 Control Register
Address: 28
23
Res
15
Res
7
Res
22
Res
14
Res
6
MECH
21
Res
13
Res
5
Res
20
Res
12
Res
4
INTL
19
Res
11
Res
3
SYNC
18
Res
10
Res
2
NOCPU
17
Res
9
Res
1
NOOSC
16
Res
8
STOP
0
STEP
Default** = 0x000000
50
STOP
Res
MECH
INTL
SYNC
NOCPU
NOOSC
STEP
1 = used to terminate the new EEBOOT sequence.
Reserved. These bits must be set to zero.
1 = widens EOUT and EDIR pulses for mechanical counters.
1 = converts the INT output to open drain configuration.
1 = forces internal A/D converter clock to synchronize to the initiation of a conversion command.
1 = converts the CPUCLK output to a one-bit output port. Reduces power consumption.
1 = saves power by disabling the crystal oscillator for external drive.
1 = enables stepper-motor signals on the EOUT/EDIR pins.
DS487F5
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相关代理商/技术参数 |
参数描述 |
|---|---|
| CS5460A-BSZ | 制造商:Cirrus Logic 功能描述:Driver IC 制造商:Cirrus Logic 功能描述:IC ENERGY METERING 1PHASE 24SSOP 制造商:Cirrus Logic 功能描述:IC, ENERGY METERING, 1PHASE, 24SSOP |
| CS5460A-BSZR | 功能描述:电流和电力监控器、调节器 IC Sngl-Phs BiDirect PWR/Energy RoHS:否 制造商:STMicroelectronics 产品:Current Regulators 电源电压-最大:48 V 电源电压-最小:5.5 V 工作温度范围:- 40 C to + 150 C 安装风格:SMD/SMT 封装 / 箱体:HPSO-8 封装:Reel |
| CS5460-BS | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Cirrus Logic 功能描述: |
| CS5460C-ISZ | 功能描述:电流和电力监控器、调节器 Sngl-Phs Bi-Drctnl Power/Energy RoHS:否 制造商:STMicroelectronics 产品:Current Regulators 电源电压-最大:48 V 电源电压-最小:5.5 V 工作温度范围:- 40 C to + 150 C 安装风格:SMD/SMT 封装 / 箱体:HPSO-8 封装:Reel |
| CS5460C-ISZR | 功能描述:电流和电力监控器、调节器 IC Sngl-Phs BiDirect PWR/Energy RoHS:否 制造商:STMicroelectronics 产品:Current Regulators 电源电压-最大:48 V 电源电压-最小:5.5 V 工作温度范围:- 40 C to + 150 C 安装风格:SMD/SMT 封装 / 箱体:HPSO-8 封装:Reel |
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