参数资料
型号: CS61884-IB
厂商: CIRRUS LOGIC INC
元件分类: 数字传输电路
英文描述: Octal T1/E1/J1 Line Interface Unit
中文描述: DATACOM, PCM TRANSCEIVER, PBGA160
封装: FBGA-160
文件页数: 33/72页
文件大小: 1474K
代理商: CS61884-IB
CS61884
DS485PP4
33
As illustrated in
Figure 13
, the ACB consists of a
R/W bit, address field, and two reserved bits. The
R/W bit specifies if the current register access is a
read (R/W = 1) or a write (R/W = 0) operation. The
address field specifies the register address from
0x00 to 0x1f.
13.3 Parallel Port Operation
Parallel port host mode operation is selected when
the MODE pin is high. In this mode, the CS61884
register set is accessed using an 8-bit, multiplexed
bidirectional address/data bus D[7:0]. Timing over
the parallel port is independent of the transmit and
receive system timing.
The device is compatible with both Intel and Mo-
torola bus formats. The Intel bus format is selected
when the MOT/INTL pin is high and the Motorola
bus format is selected when the MOT/INTL pin is
low. In either mode, the interface can have the ad-
dress and data multiplexed over the same 8-bit bus
or on separate busses. This operation is controlled
with the MUX pin; MUX = 1 means that the paral-
lel port has its address and data multiplexed over
the same bus; MUX = 0 defines a non-multiplexed
bus. The timing for the different modes are shown
in
Figure 26
,
Figure 27
,
Figure 28
,
Figure 29
,
Figure 30
,
Figure 31
,
Figure 32
and
Figure 33
.
Non-multiplexed Intel and Motorola modes are
shown in
Figure 30
,
Figure 31
,
Figure 32
and
Figure 33
. The CS pin initiates the cycle, followed
by the DS, RD or WR pin. Data is latched into or
out of the part using the rising edge of the DS, WR
or RD pin. Raising CS ends the cycle.
Multiplexed Intel and Motorola modes are shown
in
Figure 26
,
Figure 27
,
Figure 28
and
Figure 29
.A
read or write is initiated by writing an address byte
to D[7:0]. The device latches the address on the
falling edge of ALE(AS). During a read cycle, the
register datais output during thelater portion of the
RD or DS pulses. The read cycle is terminated and
the bus returns to a high impedance state as RD
transitions high in Intel timing or DS transitions
high in Motorola timing. During a write cycle, val-
id write datamust be present and held stableduring
the WR or DS pulses.
In Intel mode, the RDY output pin is normally in a
high impedance state; it pulses low once to ac-
knowledgethatthechip hasbeen selected,and high
again to acknowledge that data has been written or
read. In Motorola mode, the ACK pin performs a
similar function; it drives high to indicate that the
address has been received by the part, and goes low
again to indicate that data has been written or read.
CS
SDI
SCLK
SDO
CLKE=0
0
R/W
0
0
0
0
0
1
D0
D1
D2
D5
D3
D6
D4
D7
D0
D1
D2
D5
D3
D6
D4
D7
Address/Command Byte
Data Input/Output
Figure 13. Serial Read/Write Format (SPOL = 0)
相关PDF资料
PDF描述
CS61884-IQ Octal T1/E1/J1 Line Interface Unit
CS62180A Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
CS62180 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
CS62180B Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
CS62180B-IL Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
相关代理商/技术参数
参数描述
CS61884-IQ 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:Octal T1/E1/J1 Line Interface Unit
CS61884-IQZ 功能描述:网络控制器与处理器 IC IC Octal T1/E1/J1 Line Interface Unit RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流(最大值):595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray
CS61884-IQZR 功能描述:网络控制器与处理器 IC IC Octal T1/E1/J1 Line Interface Unit RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流(最大值):595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray
CS61884-IRZ 功能描述:网络控制器与处理器 IC IC Octal T1/E1/J1 Line Interface Unit RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流(最大值):595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray
CS61884-IRZR 功能描述:网络控制器与处理器 IC IC Octal T1/E1/J1 Line Interface Unit RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流(最大值):595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray