参数资料
型号: CS61884-IRZ
厂商: Cirrus Logic Inc
文件页数: 24/72页
文件大小: 0K
描述: IC LN INTERF T1/E1/J1 160-LFBGA
标准包装: 126
功能: 线路接口单元(LIU)
接口: E1,J1,T1
电路数: 8
电源电压: 3.14 V ~ 3.47 V
功率(瓦特): 1.73W
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 160-LFBGA
供应商设备封装: 160-TFGBA(13x13)
包装: 散装
包括: AMI 编码器和解码器,B8ZS 编码器和解码器,HDB3 编码器和解码器,LOS 检测
产品目录页面: 759 (CN2011-ZH PDF)
其它名称: 598-1717
CS61884
30
DS485F3
12.3 Digital Loopback
Digital Loopback causes the TCLK, TPOS, and
TNEG (or TDATA) inputs to be looped back
through the jitter attenuator (if enabled) to the
RCLK, RPOS, and RNEG (or RDATA) outputs.
The receive line interface is ignored, but data at
TPOS and TNEG (or TDATA) continues to be
transmitted to the line interface at TTIP and
TRING (Refer to Figure 10 on page 31).
Digital Loopback is only available during host
mode. It is selected using the appropriate bit in the
NOTE: TAOS can also be used during the Digital Loop-
back operation for the selected channel (Refer
12.4 Remote Loopback
In remote loopback, the RPOS/RNEG and RCLK
outputs are internally input to the transmit circuits
for output on TTIP/TRING. In this mode the
TCLK, TPOS and TNEG inputs are ignored. (Refer
to Figure 12 on page 31). In hardware mode, Re-
mote Loopback is selected by driving the LOOP
pin for a certain channel low. In host mode, Remote
Loopback is selected for a given channel by writing
a one to the appropriate bit in the Remote Loop-
NOTE: In hardware mode, Remote Loopback over-
rides TAOS for the selected channel. In host
mode, TAOS overrides Remote Loopback.
Encoder
Decoder
TTIP
TRING
RTIP
RRING
TNEG
TCLK
RNEG
RCLK
TPOS
RPOS
Clock Recovery &
Data Recovery
Transmit
Control &
Pulse Shaper
Jitter
Attenuator
Jitter
Attenuator
Figure 8. Analog Loopback Block Diagram
Encoder
Decoder
TNEG
TCLK
RNEG
RCLK
TPOS
RPOS
TAOS
MCLK
(All One's)
TTIP
TRING
RTIP
RRING
Clock Recovery &
Data Recovery
Transmit
Control &
Pulse Shaper
Jitter
Attenuator
Jitter
Attenuator
Figure 9. Analog Loopback with TAOS Block Diagram
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