参数资料
| 型号： | CS61884-IRZ |
| 厂商： | Cirrus Logic Inc |
| 文件页数： | 42/72页 |
| 文件大小： | 0K |
| 描述： | IC LN INTERF T1/E1/J1 160-LFBGA |
| 标准包装： | 126 |
| 功能： | 线路接口单元（LIU） |
| 接口： | E1，J1，T1 |
| 电路数： | 8 |
| 电源电压： | 3.14 V ~ 3.47 V |
| 功率（瓦特）： | 1.73W |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 160-LFBGA |
| 供应商设备封装： | 160-TFGBA（13x13） |
| 包装： | 散装 |
| 包括： | AMI 编码器和解码器，B8ZS 编码器和解码器，HDB3 编码器和解码器，LOS 检测 |
| 产品目录页面： | 759 (CN2011-ZH PDF) |
| 其它名称： | 598-1717 |
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CS61884
DS485F3
47
16.1.11 Select-IR-Scan
This is a temporary controller state. The test data
register selected by the current instruction retains
its previous state.
16.1.12 Capture-IR
In this controller state, the instruction register is
loaded with a fixed value of “01” on the rising edge
of TCK. This supports fault-isolation of the board-
level serial test data path.
16.1.13 Shift-IR
In this state, the shift register contained in the in-
struction register is connected between TDI and
TDO and shifts data one stage towards its serial
output on each rising edge of TCK.
16.1.14 Exit1-IR
This is a temporary state. The test data register se-
lected by the current instruction retains its previous
value.
16.1.15 Pause-IR
The pause state allows the test controller to tempo-
rarily halt the shifting of data through the instruc-
tion register.
16.1.16 Exit2-IR
This is a temporary state. The test data register se-
lected by the current instruction retains its previous
value.
16.1.17 Update-IR
The instruction shifted into the instruction register
is latched into the parallel output from the shift-reg-
ister path on the falling edge of TCK. When the
new instruction has been latched, it becomes the
current instruction. The test data registers selected
by the current instruction retain their previous val-
ue.
16.2 Instruction Register (IR)
The 3-bit Instruction register selects the test to be
performed and/or the data register to be accessed.
The valid instructions are shifted in LSB first and
are listed in Table 10:
16.2.1 EXTEST
The EXTEST instruction allows testing of off-chip
circuitry and board-level interconnect. EXTEST
connects the BSR to the TDI and TDO pins.
16.2.2 SAMPLE/PRELOAD
The SAMPLE/PRELOAD instruction samples all
device inputs and outputs. This instruction places
the BSR between the TDI and TDO pins. The BSR
is loaded with samples of the I/O pins by the Cap-
ture-DR state.
16.2.3 IDCODE
The IDCODE instruction connects the device iden-
tification register to the TDO pin. The device iden-
tification code can then be shifted out TDO using
the Shift-DR state.
16.2.4 BYPASS
The BYPASS instruction connects a one TCK de-
lay register between TDI and TDO. The instruction
is used to bypass the device.
Table 10. JTAG Instructions
IR CODE
INSTRUCTION
000
EXTEST
100
SAMPLE/PRELOAD
110
IDCODE
111
BYPASS
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