参数资料
型号: CS61884-IRZ
厂商: Cirrus Logic Inc
文件页数: 41/72页
文件大小: 0K
描述: IC LN INTERF T1/E1/J1 160-LFBGA
标准包装: 126
功能: 线路接口单元(LIU)
接口: E1,J1,T1
电路数: 8
电源电压: 3.14 V ~ 3.47 V
功率(瓦特): 1.73W
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 160-LFBGA
供应商设备封装: 160-TFGBA(13x13)
包装: 散装
包括: AMI 编码器和解码器,B8ZS 编码器和解码器,HDB3 编码器和解码器,LOS 检测
产品目录页面: 759 (CN2011-ZH PDF)
其它名称: 598-1717
CS61884
46
DS485F3
16.1.4 Select-DR-Scan
This is a temporary controller state.
16.1.5 Capture-DR
In this state, the Boundary Scan Register captures
input pin data if the current instruction is EXTEST
or SAMPLE/PRELOAD.
16.1.6 Shift-DR
In this controller state, the active test data register
connected between TDI and TDO, as determined
by the current instruction, shifts data out on TDO
on each rising edge of TCK.
16.1.7 Exit1-DR
This is a temporary state. The test data register se-
lected by the current instruction retains its previous
value.
16.1.8 Pause-DR
The pause state allows the test controller to tempo-
rarily halt the shifting of data through the current
test data register.
16.1.9 Exit2-DR
This is a temporary state. The test data register se-
lected by the current instruction retains its previous
value.
16.1.10 Update-DR
The Boundary Scan Register is provided with a
latched parallel output to prevent changes while
data is shifted in response to the EXTEST and
SAMPLE/PRELOAD instructions. When the TAP
controller is in this state and the Boundary Scan
Register is selected, data is latched into the parallel
output of this register from the shift-register path
on the falling edge of TCK. The data held at the
latched parallel output changes only in this state.
1
0
Test-Logic-Reset
Run-Test/Idle
Select-DR-Scan
Capture-DR
Shift-DR
Exit1-DR
Pause-DR
Exit2-DR
Update-DR
Select- I R-Scan
Capture- IR
Shift- IR
Exit1- IR
Pause- IR
Exit2- IR
Update- I R
0
11
1
11
1
11
1
0
00
0
1
0
Figure 16. TAP Controller State Diagram
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