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参数资料
| 型号： | CS62180 |
| 厂商： | Cirrus Logic, Inc. |
| 元件分类： | 通信及网络 |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件页数： | 18/50页 |
| 文件大小： | 411K |
| 代理商： | CS62180 |
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Transmit Transparent Registers (TTR)
The Transmit Transparent Registers allow indi-
vidual DS0 channels to be programmed clear,
disabling robbed bit signaling and B7 zero sup-
pression for that channel (if selected, B8ZS is
unaffected by transparent channels). There are 3
TTR registers: TTR1, TTR2, and TTR3. Each bit
in the TTR registers corresponds to a DS0 chan-
nel: TTR1.0 = channel 1, TTR1.7 = channel 8,
TTR2.7 = channel 16, etc. A channel is pro-
grammed clear by setting the bit which
corresponds to that channel in the appropriate
TTR register. See Figure 11.
Transmit Idle Registers (TIR)
By setting the appropriate bits in the Transmit
Idle Registers, individual DS0 channels can be
replaced with the idle code selected via TCR.3
(see above). If the idle channel is not also pro-
grammed clear (via TTR1 - TTR3), the code
may be corrupted during signaling frames if
robbed bit signaling is enabled (TCR.4 = 1).
There are 3 TIR registers: TIR1, TIR2, and
TIR3. Each bit in the TIR registers corresponds
to a DS0 channel: TIR1.0 = channel 1, TIR1.7 =
channel 8, TIR2.7 = channel 16, etc. A channel
is programmed idle by setting the bit which cor-
responds to that channel in the appropriate TIR
register. See Figure 12.
Transmission Insertion Hierarchy
Figures 13a - 13c give an overview of the deci-
sion hierarchy which determines the final
composition of the output stream. It shows the
various control options as inputs into decision
branches of the flow chart, and the order in
which the various optional signals are muxed
into the final data stream.
7
(MSB)
CH8
CH16
CH24
"0" = Normal
6
5
4
3
2
1
0
(LSB)
CH1
CH9
CH17
TIR1
TIR2
TIR3
CH7
CH15
CH23
"1" = Corresponding DS0 Channel is Replaced with Idle Code. (See TCR.3)
CH6
CH14
CH22
CH5
CH13
CH21
CH4
CH12
CH20
CH3
CH11
CH19
CH2
CH10
CH18
Figure 12. Transmit Idle Registers (TIR1 - TIR3)
7
(MSB)
CH8
CH16
CH24
"0" = Normal
6
5
4
3
2
1
0
(LSB)
CH1
CH9
CH17
TTR1
TTR2
TTR3
CH7
CH15
CH23
"1" = Corresponding DS0 Channel is Transparent. (Not signaling or B7 Insertion.)
CH6
CH14
CH22
CH5
CH13
CH21
CH4
CH12
CH20
CH3
CH11
CH19
CH2
CH10
CH18
Figure11. Transmit Transparent Registers (TTR1 - TTR3)
CS62180B
18
DS225PP
2
相关PDF资料 |
PDF描述 |
|---|---|
| CS62180B | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| CS62180B-IL | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| CS62LS4008GC | Low Power CMOS SRAM 512K X 8 Bits |
| CS62LS4008GI | Low Power CMOS SRAM 512K X 8 Bits |
| CS62LS4008HC | Low Power CMOS SRAM 512K X 8 Bits |
相关代理商/技术参数 |
参数描述 |
|---|---|
| CS62180A | 制造商:未知厂家 制造商全称:未知厂家 功能描述:T1 Framer |
| CS62180A-IL | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Framer/Formatter |
| CS62180A-IP | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Framer/Formatter |
| CS62180B | 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:T1 FRAMER |
| CS62180B-IL | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cirrus Logic 功能描述: |
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