参数资料
型号: CS62180
厂商: Cirrus Logic, Inc.
元件分类: 通信及网络
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件页数: 26/50页
文件大小: 411K
代理商: CS62180
When the receiver initiates an auto resync,
RSIGFR is held low, but all other output timing
will continue in the old alignment until the new
framing is found. When the new framing align-
ment is qualified, the output timing will change
to the new alignment at the beginning of the next
superframe (or at the start of frame 13 in SLC-
96
mode), and RLOS will return low one bit
period before the F-bit of the second frame.
A receiver resync has no effect on the transmit
side timing or configuration, and behavior of the
output timing and RLOS pin is the same as that
for an auto resync described above. This is in
contrast to a reset initiated via the RST pin,
which clears all internal registers on the falling
edge, including the transmit side registers, resets
the output timing while RST is low, and then in-
itiates a receiver resync on the rising edge.
The time it takes the receiver to resync depends
on resync algorithm selected via RCR.2 and
RCR.3. The remaining bits in the RCR (1, 6, and
7) determine under what conditions an automatic
resync will be initiated.
Forced Resync
RCR.0: RESYNC
RESYNC (RCR.0) can be used to force a re-
ceiver resync. Toggling RCR.0 will initiate a
resync immediately on the rising edge. It must
then be cleared and set again to initiate another
resync. Toggling RCR.0 when going into loop-
back mode will force the receiver to resync to
the new frame alignment immediately. This is
faster than waiting for the internal hardware to
recognize an out-of-frame (OOF) condition and
initiating an automatic resync.
Note: A forced resync should be issued after a
change in framing mode to insure correct syn-
chronization.
Auto Resync Conditions
RCR.1: SYNCE
RCR.6: OOF
RCR.7: ARC
SYNCE (RCR.1) can be set to a "1" to com-
pletely disable automatic resync. If RCR.1 is
clear, a resync will automatically be initiated
when the conditions specified by RCR.6 and
RCR.7 are detected.
OOF (RCR.6) specifies how many framing bits
(F
T
or FPS channels only) must be in error be-
fore the receiver declares an out-of-frame (OOF)
condition. A resync is always initiated (unless
disabled) when an OOF is detected. If RCR.6 is
clear, an OOF is declared if 2 out of 4 F
T
or FPS
bits are in error. If RCR.6 is set to a one, an
OOF is declared if 2 out of 5 framing bits are
errored. Note that the setting of RCR.6 also ef-
fects the reporting of OOF events to the Receive
Status Register (RSR) and Error Count Register
(ECR). Refer to the appropriate sections below
for details.
ARC (RCR.7) declares whether the receiver will
initiate a resync on an OOF event only, or resync
on both OOF and carrier loss (RCL). If RCR.7 is
cleared, the receiver will commence resync upon
detection of either an OOF event (as defined by
RCR.6 above), or an RCL. If RCR.7 is set, the
receiver will only resync in response to an OOF
condition.
Resync Algorithm
RCR.2: SYNCT
RCR.3: SYNCC
SYNCT (RCR.2) allows you to declare how
many bits must be qualified in the framing pat-
tern before the receiver declares synchronization.
When RCR.2 is clear, 10 consecutive F
T
or FPS
framing bits preceding an RMSYNC rising edge
must be qualified. Setting RCR.2 to a "1" re-
quires the CS62180B to qualify
24 consecutive
F
T
or FPS bits preceding an
RMSYNC
CS62180B
26
DS225PP
2
相关PDF资料
PDF描述
CS62180B Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
CS62180B-IL Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
CS62LS4008GC Low Power CMOS SRAM 512K X 8 Bits
CS62LS4008GI Low Power CMOS SRAM 512K X 8 Bits
CS62LS4008HC Low Power CMOS SRAM 512K X 8 Bits
相关代理商/技术参数
参数描述
CS62180A 制造商:未知厂家 制造商全称:未知厂家 功能描述:T1 Framer
CS62180A-IL 制造商:未知厂家 制造商全称:未知厂家 功能描述:Framer/Formatter
CS62180A-IP 制造商:未知厂家 制造商全称:未知厂家 功能描述:Framer/Formatter
CS62180B 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:T1 FRAMER
CS62180B-IL 制造商:Rochester Electronics LLC 功能描述: 制造商:Cirrus Logic 功能描述: