- 您现在的位置：买卖IC网 > PDF目录380086 > CS62180 (Cirrus Logic, Inc.) Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 PDF资料下载
参数资料
| 型号： | CS62180 |
| 厂商： | Cirrus Logic, Inc. |
| 元件分类： | 通信及网络 |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件页数： | 36/50页 |
| 文件大小： | 411K |
| 代理商： | CS62180 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页当前第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页
Power Supply Connections
VDD - Positive Supply, Pin 40 (PLCC, Pin 44).
Positive digital power supply. Nominally +5.0 Volts.VDD current requirements increase if
RCLK is static, and if RST is held high.
VSS - Signal Ground, Pin 20 (PLCC, Pin 22).
Power supply ground. Nominally 0 volts.
Host Mode Serial Interface
Pins 14 - 18 (PLCC, 16 - 20) are multifunctional. When in Host mode, they operate as serial
interface pins. When in hardware mode, they are redefined as mode control pins. Their hard-
ware mode operation is described separately under
Hardware Mode Control Pins
, below.
SPS - Serial Port Select, Pin 19 (PLCC, Pin 21).
Must be tied to VDD to select host mode, allowing operation of serial port. Tying SPS to VSS
selects hardware mode. Selecting hardware mode clears all internal registers except the com-
mon control register (CCR) and transmitter control register (TCR), and redefines pins 14
through 18 (PLCC, 16 - 20) as mode control pins.
Inputs
SDI - Serial Data In, Pin 15 (PLCC, Pin 17).
Serial data input for addressing and writing to on-board control registers. Data is input LSB
first. Input data is latched on the rising edge of SCLK.
CS - Chip Select, Pin 17 (PLCC, Pin 19).
CS low enables serial port for read or write. When CS transitions high, all data transfers are
terminated, port control logic is disabled, and SDO is tri-stated to allow for multiprocessor
interface.
SCLK - Serial Data Clock, Pin 18 (PLCC, Pin 20).
Used to read or write the serial port. Data at SDO is output on the falling edge of SCLK and
held to the next falling edge. Input data on SDI is latched on the rising edge of SCLK.
Outputs
INT - Receive Alarm Interrupt, Pin 14 (PLCC, Pin 16).
Pulled low to flag host controller when an alarm interrupt condition occurs. The user may select
which alarm conditions will trigger an interrupt by appropriately setting the Receive Interrupt
Mask Register (RIMR). INT is an open drain output, and should be tied to the positive supply
(VDD) through a resistor.
CS62180B
36
DS225PP
2
相关PDF资料 |
PDF描述 |
|---|---|
| CS62180B | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| CS62180B-IL | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| CS62LS4008GC | Low Power CMOS SRAM 512K X 8 Bits |
| CS62LS4008GI | Low Power CMOS SRAM 512K X 8 Bits |
| CS62LS4008HC | Low Power CMOS SRAM 512K X 8 Bits |
相关代理商/技术参数 |
参数描述 |
|---|---|
| CS62180A | 制造商:未知厂家 制造商全称:未知厂家 功能描述:T1 Framer |
| CS62180A-IL | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Framer/Formatter |
| CS62180A-IP | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Framer/Formatter |
| CS62180B | 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:T1 FRAMER |
| CS62180B-IL | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cirrus Logic 功能描述: |
发布紧急采购，3分钟左右您将得到回复。