参数资料
型号: CS62180
厂商: Cirrus Logic, Inc.
元件分类: 通信及网络
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件页数: 32/50页
文件大小: 411K
代理商: CS62180
Violation received will cause BVCS (RSR.7) to
be set to a "1". The BVCR can be preset, to a
value greater than 0, to lower the threshold at
which it saturates and signals an alarm in RSR.7.
Bipolar Violations in valid B8ZS codes are never
counted by the CS62180B
. Note also that the
Bipolar Violation monitoring circuit is disabled
entirely when using NRZ input at
RPOS/RNEG (selected by tying RPOS/RNEG
together).
Individual Bipolar Violations are also reported in
real time on RBV (pin 37). RBV will go high
simultaneously with the output of the accused bit
at RSER. It will only be held for that bit period,
falling at the next bit, unless another violation is
detected.
Interrupts
When operating in host mode, an interrupt pin,
INT (pin 14), is provided to signal the host proc-
essor of alarm conditions. INT is an open drain
output, and should be tied to the positive supply
through a resistor. The INT pin can be pro-
grammed to respond whenever any bit of the
Receive Status Register (RSR) goes high by set-
ting the corresponding bit of the Receive
Interrupt Mask Register (RIMR). Each bit of the
RIMR is ’AND’ed with the corresponding bit of
the RSR to determine the interrupt. Clearing any
bit in the RIMR will disable the interrupt for that
alarm condition. When an interrupt has been sig-
naled, the CS62180B must be
serviced by the
host processor to clear the alarm,
as described below.
Figure 25 shows an overview
of the RIMR.
Alarm Servicing
The CS62180B must be serviced
by the host processor to clear the interrupt.
Clearing the appropriate bit (or bits, if more than
1 alarm condition exists) in the Receive Interrupt
Mask Register (RIMR) will clear any interrupt
unconditionally. The interrupt for that alarm will
remain disabled until the bit in the RIMR is set
again.
Depending on the type of alarm condition, an in-
terrupt may also be cleared without changing the
RIMR. If the alarm is in response to a counter
saturation (see
Bipolar Violation Count Satura-
tion
and
Error Count Saturation
, above), then
the counter must be reset to a value other than
all "1’s" to clear the alarm. If the interrupt is in
response to a real time event, then it may be
cleared by a
direct
read (a burst read will have
no effect) of the RSR. Note that reading the RSR
will only clear the interrupt if the alarm condi-
tion no longer persists. For real time events of
long duration, clearing the appropriate bits in the
RIMR is the only way to clear the interrupt.
7
(MSB)
BVCS
6
5
4
3
2
1
0
(LSB)
ECS
RYEL
Disables interrupts for the corresponding bit of the RSR.
Enables an interrupt whenever the corresponding bit of the RSR goes high.
RCL
FERR
B8ZSD
RBL
RLOS
0
1
Figure 25. Receive Interrupt Mask Register (RIMR)
7
(MSB)
BVD7
6
5
4
3
2
1
0
(LSB)
BVD6
Counts individual Bipolar Violations. Sets RSR.7 high when overfolws past 255 (11111111).
Presetable to any starting value to limit the number of Bipolar Violations needed to overflow.
BVD5
BVD4
BVD3
BVD2
BVD1
BVD0
Figure 24. Bipolar Violation Count Register (BVCR)
CS62180B
32
DS225PP
2
相关PDF资料
PDF描述
CS62180B Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
CS62180B-IL Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
CS62LS4008GC Low Power CMOS SRAM 512K X 8 Bits
CS62LS4008GI Low Power CMOS SRAM 512K X 8 Bits
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相关代理商/技术参数
参数描述
CS62180A 制造商:未知厂家 制造商全称:未知厂家 功能描述:T1 Framer
CS62180A-IL 制造商:未知厂家 制造商全称:未知厂家 功能描述:Framer/Formatter
CS62180A-IP 制造商:未知厂家 制造商全称:未知厂家 功能描述:Framer/Formatter
CS62180B 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:T1 FRAMER
CS62180B-IL 制造商:Rochester Electronics LLC 功能描述: 制造商:Cirrus Logic 功能描述: