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参数资料
| 型号： | CS62180 |
| 厂商： | Cirrus Logic, Inc. |
| 元件分类： | 通信及网络 |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件页数： | 40/50页 |
| 文件大小： | 411K |
| 代理商： | CS62180 |
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Receiver
Inputs
RCLK - Receive Clock, Pin 24 (PLCC, Pin 27).
1.544 MHz primary receiver clock. Receiver data is output on the rising edge, and input on the
falling edge of RCLK. If no signal is present on RCLK, RST should be held low to minimize
power consumption.
RPOS, RNEG - Receive Bipolar Data Inputs, Pins 34 and 35 (PLCC, Pins 38 and 39).
Recovered data, sampled on falling edge of RCLK. Tie pins together to receive NRZ data and
disable bipolar violation monitoring circuitry. Delay from RPOS/RNEG to output at RSER is
13 RCLK periods.
RST - Reset, Pin 33 (PLCC, Pin 37).
Falling edge of RST clears all internal registers and resets receiver error counters. A receiver
resync is forced when RST returns high. This resync effects only the receiver synchronization,
and has no effect on transmit timing, but transmit control modes are cleared. The host processor
should restore all control modes following a reset by writing the appropriate control registers.
NOTE:
On system power-up,
RST
must be held low to insure initialization of all on-board
registers.
Outputs
RYEL - Receive Yellow Alarm, Pin 21 (PLCC, Pin 23).
Transitions high when a yellow alarm is detected, returns low when yellow alarm is cleared.
When in Host mode, Yellow alarm formats for both 193S and 193E modes can be selected via
bits 3 and 5 of the Common Control Register. When in hardware mode, the 193S mode defaults
to bit 2 Yellow alarms, and the 193E mode defaults to FDL yellow alarms. Refer to bit 5 of the
Receive Status Register (RYEL) for a description of alarm detection conditions.
RCL - Receive Carrier Loss, Pin 36 (PLCC, Pin 40).
On the CS62180B, RCL transitions high if 1281 consecutive "0’s" are detected on RPOS
and RNEG and returns low on the next "1".
RBL - Receive Blue Alarm, (CS62180B PLCC only, Pin 3).
Transitions high on a frame boundary if an unframed-all ones and an out-of-frame condition
simultaneously occur. Returns low when either out-of-frame ends or zeros are detected.
RBV - Receive Bipolar Violation, Pin 37 (PLCC, Pin 41).
If a bipolar violation is detected, RBV goes high simultaneous with output of accused bit on
RSER, low otherwise.
CS62180B
40
DS225PP
2
相关PDF资料 |
PDF描述 |
|---|---|
| CS62180B | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| CS62180B-IL | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| CS62LS4008GC | Low Power CMOS SRAM 512K X 8 Bits |
| CS62LS4008GI | Low Power CMOS SRAM 512K X 8 Bits |
| CS62LS4008HC | Low Power CMOS SRAM 512K X 8 Bits |
相关代理商/技术参数 |
参数描述 |
|---|---|
| CS62180A | 制造商:未知厂家 制造商全称:未知厂家 功能描述:T1 Framer |
| CS62180A-IL | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Framer/Formatter |
| CS62180A-IP | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Framer/Formatter |
| CS62180B | 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:T1 FRAMER |
| CS62180B-IL | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cirrus Logic 功能描述: |
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