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参数资料
| 型号： | CS62180B |
| 厂商： | Cirrus Logic, Inc. |
| 元件分类： | 通信及网络 |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件页数： | 29/50页 |
| 文件大小： | 411K |
| 代理商： | CS62180B |
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Each of the eight bits of the RSR (Figure 21)
corresponds to an alarm condition. A bit in the
RSR is set when the corresponding alarm is de-
tected. It will be cleared by a direct read (a burst
read will have no effect) of the RSR, unless the
alarm condition persists (see Alarm Servicing,
below). TCLK is used to clock the internal cir-
cuitry which clears RSR after it is directly read;
therefore, a 1.544 MHz signal must always be
input to TCLK, even for a "receiver-only" appli-
cation. The status pins which correspond to
many of the RSR bits operate in real time. They
go high when the error is detected, and return
low either immediately, or as soon as the error
condition is cleared. Alarms are reported syn-
chronously with the emergence of the offending
bits on RSER. See Figure 22, and the corre-
sponding alarm description below for further
description of status pin timing.
Receive Loss of Sync
RSR.0: RLOS
RLOS (RSR.0) goes high when a receiver resync
is in progress. When the receiver is set to auto
resync (RCR.1 = 0), the receiver will commence
resync when an OOF event or loss of carrier is
detected. If in response to an OOF, RLOS transi-
tions high synchronously with the output of the
offending F-bit on RSER (see RCR.6).
If in response to an RCL,
RLOS goes high
with
the 128th
±
1 consecutive
zero bit.
The RLOS pin will return low one bit period
prior to the F-bit of the second frame after the
new alignment has been declared (timing signals
will reset at the start of the new superframe). Re-
fer to
Receiver Synchronization
, above, for more
information.
Receive Blue Alarm
RSR.1: RBL
RBL (RSR.1) will transition high when a blue
alarm is detected, and is updated at the begin-
ning of odd-numbered frames.
A blue alarm is reported when
ever
unframed all ones occurs, as per Bellcore
TR-TSY-000191. The algorithm used is to simul-
taneously check for an out-of-frame (OOF)
condition, and check for 14 or less zeros out of
13,895 bits. All bits, including frame bits, are
tested. RBL goes high on a frame boundary.
RBL goes low immediately (indicating the termi-
nation of the AIS condition) if OOF goes low, or
if 15 or more zeros are counted and the number
of bit periods is less than or equal to 13,895.
RBL is reported on pin 3 of the 44-pin PLCC
package. There is no status pin corresponding to
RBL on the 40-pin DIP package.
B8ZS/COFA Detect
RSR.2: B8ZSD
B8ZSD (RSR.2) is a multifunction bit. It can be
configured either to report the detection of B8ZS
codes, or to indicate a change of framing align-
ment. This selection is performed through the
setting of CCR.6 (see Common Control Register,
above). There is no status pin corresponding to
RSR.2.
If CCR.6 is clear, RSR.2 will go high every time
a B8ZS code is detected in the incoming T1
data. This detector remains operational, whether
or not B8ZS substitution has been enabled via
CCR.2.
CS62180B
DS225PP
2
29
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| CS62180B-IL | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| CS62LS4008GC | Low Power CMOS SRAM 512K X 8 Bits |
| CS62LS4008GI | Low Power CMOS SRAM 512K X 8 Bits |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| CS62180B-IL | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cirrus Logic 功能描述: |
| CS62180B-IL/C | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cirrus Logic 功能描述: |
| CS62180B-ILR | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cirrus Logic 功能描述: |
| CS62180B-IP | 制造商:Cirrus Logic 功能描述:T1 FRAMER - Rail/Tube |
| CS6224A | 制造商:Cypress Semiconductor 功能描述: |
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