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参数资料
| 型号： | CS62180B |
| 厂商： | Cirrus Logic, Inc. |
| 元件分类： | 通信及网络 |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件页数： | 31/50页 |
| 文件大小： | 411K |
| 代理商： | CS62180B |
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When using a bit 2 yellow alarm, in either 193S
or 193E mode, a yellow alarm is defined as a
"0" in bit 2 (2nd MSB) of every DS0 channel.
RYEL will signal a bit 2 yellow alarm when 256
or more consecutive channels are detected with a
"0" in bit 2. The alarm will clear at the next "1"
detected in a bit 2 position.
When using an FDL yellow alarm in 193E
mode, RYEL will declare a yellow alarm after
16 repetitions of "00FF" on the FDL. The alarm
will clear at the next bit which is out of se-
quence.
When using an S-bit yellow alarm in 193S
mode, RYEL will transition high whenever a "1"
is detected in the F-bit of frame 12. The alarm is
not cleared until a zero is detected in the F-bit of
frame 12.
In T1DM mode , a yellow alarm is detected by
checking the channel 24 sync word. In SLC-96
mode, the CS62180B does not recognize yellow
alarms, rather, they are recognized by the user
via the DL.
Error Count Saturation
RSR.6: ECS
ECS (RSR.6) monitors the status of the Error
Count Register (ECR), as shown in Figure 23.
The ECR provides two, separate, 4 bit counters
at one register address: the ESF Error Count (D0
- D3), and the OOF Count (D4 - D7). RSR.6
will go high after either of these 4 bit counters
becomes saturated (at 15), and new OOF or ESF
event is detected (the 16
th
or greater).
The OOF Counter (D4 - D7) records the number
of out-of-frame events. An OOF event occurs
when 2 out of either 4 or 5 consecutive framing
bits are in error, as defined by RCR.6. In 193S
mode, the F
T
bits are monitored for OOF events,
while in 193E mode, the FPS bits are used.
The ESF counter (D0 - D3) records the number
of "Errored Superframes". An ESF event in 193E
mode is defined as an OOF event, or a CRC er-
ror. The ESF counter will be advanced each time
either event is detected. In 193S mode, the ESF
counter records individual framing bit errors. If
RCR.3 is set, requiring F
S
bits to be qualified for
synchronization, both F
T
and F
S
bit errors will
advance the ESF counter. If RCR.3 is clear, only
F
T
bits will be monitored.
The OOF and ESF operate separately, each
counting up from 0 (hex) and saturating at F
(hex). The saturation threshold can be changed
for each counter separately, by presetting the
counter to some value higher than 0. Because
they share the same register address, both count-
ers must be read or written simultaneously.
There is no status pin directly corresponding to
the ECS bit, but FERR signals individual frame
bit and CRC errors, and RLOS signals an OOF
event. ECS counter increments are disabled
when resync is in progress (RLOS high).
Bipolar Violation Count Saturation
RSR.7: BVCS
Individual Bipolar Violations are recorded in an
8 bit counter, the Bipolar Violation Count Regis-
ter (BVCR), as show in Figure 24. The BVCR
counts up from 0 (all "0’s") to 255 (all "1’s").
After reaching saturation at 255, every Bipolar
7
(MSB)
6
5
4
3
2
1
0
(LSB)
OOFD3
OOF Count
OOFD2
OOFD1
OOFD0
ESFD3
ESF Error Count
ESFD2
ESFD1
EFSD0
Presetable.
Saturates at 15 (1111).
Presetable.
Saturates at 15 (1111).
Figure 23. Error Count Register (ECR)
CS62180B
DS225PP
2
31
相关PDF资料 |
PDF描述 |
|---|---|
| CS62180B-IL | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| CS62LS4008GC | Low Power CMOS SRAM 512K X 8 Bits |
| CS62LS4008GI | Low Power CMOS SRAM 512K X 8 Bits |
| CS62LS4008HC | Low Power CMOS SRAM 512K X 8 Bits |
| CS62LS4008HI | Low Power CMOS SRAM 512K X 8 Bits |
相关代理商/技术参数 |
参数描述 |
|---|---|
| CS62180B-IL | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cirrus Logic 功能描述: |
| CS62180B-IL/C | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cirrus Logic 功能描述: |
| CS62180B-ILR | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cirrus Logic 功能描述: |
| CS62180B-IP | 制造商:Cirrus Logic 功能描述:T1 FRAMER - Rail/Tube |
| CS6224A | 制造商:Cypress Semiconductor 功能描述: |
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