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参数资料
| 型号： | CS62180B |
| 厂商： | Cirrus Logic, Inc. |
| 元件分类： | 通信及网络 |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件页数： | 33/50页 |
| 文件大小： | 411K |
| 代理商： | CS62180B |
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HARDWARE MODE
For stand alone applications or prototyping in
which the device is to operate without a host
processor, the CS62180B can be
configured to run in hardware mode by tying the
Serial Port Select pin (SPS) to ground (VSS).
This disables the serial port and redefines pins
14-18 (16-20, PLCC) as mode control pins. All
registers are cleared, with the exception of the
control bits which are mapped to the mode con-
trol pins, and TCR.4, which is set to "1",
enabling robbed bit signaling. This means that,
with the exception of robbed bit signaling, the
configuration of the CS62180B
in hardware mode is the same as if it were in
host mode with all control bits cleared. Dynamic
control of a few of the control bits is provided
by mapping them directly to pins 14-18 (16-20,
PLCC). Operation of these pins is described in
Hardware Mode Control Pins
and Table 2. Note
that the SLC-96
and T1DM framing formats
are not supported in the hardware mode.
When operating in hardware mode, bit-robbed
signaling is enabled for all channels. Signaling
data sampled from TABCD is inserted into the
8th bit position (LSB) of every DS0 channel dur-
ing signaling frames (every 6th frame). There is
no facility for programming individual channels
clear, however; all channels may be made trans-
parent by tying TABCD to TSER.
When pulling 193SI high for external S-bit in-
sertion in 193S mode, data is sampled from
TLINK and inserted into the F-bits of even
frames. The 193SI pin has no effect when the
device is in 193E mode. When using 193E for-
mat, TLINK is sampled for insertion into every
odd F-bit (FDL). CRC data is internally gener-
ated and cannot be externally supplied.
The receiver will initiate a resync if 2 of the pre-
vious 4 framing bits were in error. It will declare
synchronization after 10 consecutive F-bits are
qualified. When in 193E mode, CRC errors will
be reported on RFER, but not used to qualify
synchronization. Receiver status can be moni-
tored via the status outputs: RYEL, RCL, RBV,
RFER, and RLOS. There is no support for gen-
erating blue alarms or idle code insertion when
in hardware mode.
Hardware Mode Control Pins
Framing Format
The FM pin allows selection of the framing
mode for both transmit and receive sides. Hold-
ing this pin low selects 193S framing mode.
193E framing may be selected by pulling the
FM pin high.
PIN NUMBER
DIP
14
REGISTER
MAPPING
TCR.2
DESCRIPTION
193S: S-bit Insertion
FUNCTION
0 = Internal
1 = External
0 = 193S
1 = 193E
0 = Disabled
1 = Enabled
0 = Transparent
1 = B7 Stuffing
0 = Disabled
1 = Enabled
PLCC
16
15
17
CCR.4
Framing Mode Select
16
18
TCR.0
Transmit Yellow Alarm
17
19
CCR.1
B7 Zero Suppression
18
20
CCR.2
B8ZS Zero Suppression
Table 2. Hardware Mode Control Pins
CS62180B
DS225PP
2
33
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相关代理商/技术参数 |
参数描述 |
|---|---|
| CS62180B-IL | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cirrus Logic 功能描述: |
| CS62180B-IL/C | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cirrus Logic 功能描述: |
| CS62180B-ILR | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cirrus Logic 功能描述: |
| CS62180B-IP | 制造商:Cirrus Logic 功能描述:T1 FRAMER - Rail/Tube |
| CS6224A | 制造商:Cypress Semiconductor 功能描述: |
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