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参数资料
| 型号： | CS62180B |
| 厂商： | Cirrus Logic, Inc. |
| 元件分类： | 通信及网络 |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件页数： | 9/50页 |
| 文件大小： | 411K |
| 代理商： | CS62180B |
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D7 (MSB) specifies burst mode if set to 1. When
using burst mode, the address field of the com-
mand word must be "0000", any other value will
invalidate the command, and the CS62180
B
will simply ignore it. This effectively
means that the command for a burst write is 80
(hex) and a burst read is 81 (hex).
Burst mode allows the sixteen registers to be
consecutively read or written. Writing all regis-
ters allows fast initialization at power-up or
system reset. (Note that the Receiver Status Reg-
ister, RSR, is read-only, so a write during burst
mode will have no effect.) When using burst
mode, registers are read or written in address or-
der, 0000 (RSR) to 1111 (RMR3). Burst mode
ends on the first rising edge of CS. See Table 1
for a complete list of the CS62180
B
on-chip registers.
ACLKI
TCLK
RCLK
RPOS
RNEG
TPOS
TNEG
CS62180B
MODE
V+
TCLK
TPOS
TNEG
RNEG
RPOS
RCLK
SCLK
SDO
SDI
TO HOST CONTROLLER
CS61535A
CS61574A or CS61575
CS
SPS
SCLK
SDO
SDI
CS
SIGNAL
CLKE
Figure 3. Interfacing to a Crystal T1 LIU.
ADDR
0000
(T) TRANSMIT
(R) RECEIVE
REGISTER NAME AND DESCRIPTION
RSR
Receive Status Register
- A read only register which reports all active receiver
alarm conditions.
RIMR
Receive Interrupt Mask Register
- A mask which allows selection of individual
alarm conditions for generation of hardware interrupt.
BVCR
Bipolar Violation Count Register
- A bipolar violation alarm is generated after
this 8 bit counter surpasses it’s user definable limit.
ECR
Error Count Register
- Two separate 4 bit counters, which record OOF errors,
and frame bit or CRC errors. Like BVCR, each can be preset to a saturation
point.
CCR
Common Control Register
- Selects global configuration options, such as:
framing mode, zero suppression, or loopback.
RCR
Receive Control Register
- Selects receiver specific options, such as the resync
algorithm or insertion of digital milliwatt codes.
TCR
Transmit Control Register
- Selects transmitter specific options, such as alarm
generation, clear or idle channel enable, and external S-bit or CRC insertion.
TIR1
TIR2
TIR3
TTR1
TTR2
TTR3
RMR1
RMR2
RMR3
R
0001
R
0010
R
0011
R
0100
T/R
0101
R
0110
T
0111
1000
1001
1010
1011
1100
1101
1110
1111
Transmit Idle Registers
- Each bit of the three TIR registers corresponds to an
individual DS0 channel. When set, that channel is replaced with an idle code.
T
Transmit Transparent Registers
- Each bit corresponds to a DS0 channel. When
set, that signaling and B7 zero suppression is disabled for that channel.
T
Receive Mark Registers
- Each bit corresponds to a DS0 channel. When set, the
channel data is replaced with an idle or digital milliwatt code.
R
Table 1. On-Chip Registers
CS62180B
DS225PP
2
9
相关PDF资料 |
PDF描述 |
|---|---|
| CS62180B-IL | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| CS62LS4008GC | Low Power CMOS SRAM 512K X 8 Bits |
| CS62LS4008GI | Low Power CMOS SRAM 512K X 8 Bits |
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| CS62LS4008HI | Low Power CMOS SRAM 512K X 8 Bits |
相关代理商/技术参数 |
参数描述 |
|---|---|
| CS62180B-IL | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cirrus Logic 功能描述: |
| CS62180B-IL/C | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cirrus Logic 功能描述: |
| CS62180B-ILR | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cirrus Logic 功能描述: |
| CS62180B-IP | 制造商:Cirrus Logic 功能描述:T1 FRAMER - Rail/Tube |
| CS6224A | 制造商:Cypress Semiconductor 功能描述: |
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