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参数资料
| 型号： | CS62180B |
| 厂商： | Cirrus Logic, Inc. |
| 元件分类： | 通信及网络 |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件页数： | 39/50页 |
| 文件大小： | 411K |
| 代理商： | CS62180B |
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TLINK - Transmit Link Data, Pin 10 (PLCC, Pin 12).
In 193S framing mode, setting bit 2 of the Transmission Control Register (TCR) enables data
on TLINK to be inserted into the S-bit channel (F-bit of all even frames). In 193E mode,
TLINK is sampled for data to be inserted into the F-bit of all odd frames for the 4 kHz facility
data link (FDL). In the SLC-96
mode, TLINK is sampled for data to be inserted into the DL.
In T1DM mode, TLINK is sampled for data to be inserted into the channel 24 "A" data link.
Delay from TLINK to TPOS/TNEG is 10 TCLK periods. In hardware mode, external S-bit
insertion on TLINK is enabled by setting pin 14 (193SI) high.
Outputs
TPOS, TNEG - Transmit Bipolar Data Outputs, Pins 12 and 13 (PLCC, Pins 14 and 15 ).
Coded data for transmission, updated on rising edge of TCLK. If TCR.7 is clear, or the
CS62180B is in hardware mode, data is output in dual-unipolar format. If
TCR.7 is set to a "1", data is output on TPOS in NRZ format, and TNEG is held low. Delay
from input to TPOS/TNEG is 10 TCLK periods.
TCHCLK - Transmit Channel Clock, Pin 4 (PLCC, Pin 5).
192 kHz clock which identifies DS0 channel boundaries. TCHCLK rises to indicate that the
next bit input on TSER is the first bit (MSB) of the DS0 channel. TCHCLK has a 50% duty
cycle.
TMO - Transmit Multiframe Out, Pin 6 (PLCC, Pin 8).
Output of internal multiframe counter. Rising edge marks beginning of multiframe, with 50%
duty cycle. Internal multiframe counter can be set on the rising edge of TMSYNC. In 193S
mode, TMO is high for frames 1-6, and low for frames 7-12, allowing easy distinction of
signaling channels A and B. In 193E mode, TMO is high for 1-12, and low for 13-24, and can
be used together with TSIGSEL to distinguish channels A, B, C, and D.
TSIGSEL - Transmit Signaling Select, Pin 7 (PLCC, Pin 9).
In 193S, 193E and T1DM modes, TSIGSEL runs at 2x TMO with a 50% duty cycle. Together
with TMO, TSIGSEL provides a way to distinguish signaling channels A, B, C, and D in 193E
mode. TMO is high for channels A and B. TSIGSEL is high for channels A and C (frames 1-6
and 13-18). In SLC-96
mode, TSIGSEL provides a way to distinquish when the DL bits are
to input.
TSIGFR - Transmit Signaling Frame, Pin 8 (PLCC, Pin 10).
TSIGFR goes high during signaling frames only, remaining low at all other times. Signaling
frames are frames 6 and 12 in 193S, SLC-96
and T1DM modes, and 6, 12, 18, and 24 in
193E mode.
TLCLK - Transmit Line Clock, Pin 11 (PLCC, Pin 13).
In 193S, 193E and SLC-96
modes, TLCLK runs at 4 kHz with a 50% duty cycle. It’s high
during odd numbered frames, and is useful for marking F
S
or FDL channel timing (input on
TLINK), and F
T
, FPS, and CRC channels (input on TSER). In T1DM, TLCLK runs at 8 kHz,
with a duty cycle of one bit period high per frame.
CS62180B
DS225PP
2
39
相关PDF资料 |
PDF描述 |
|---|---|
| CS62180B-IL | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| CS62LS4008GC | Low Power CMOS SRAM 512K X 8 Bits |
| CS62LS4008GI | Low Power CMOS SRAM 512K X 8 Bits |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| CS62180B-IL | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cirrus Logic 功能描述: |
| CS62180B-IL/C | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cirrus Logic 功能描述: |
| CS62180B-ILR | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cirrus Logic 功能描述: |
| CS62180B-IP | 制造商:Cirrus Logic 功能描述:T1 FRAMER - Rail/Tube |
| CS6224A | 制造商:Cypress Semiconductor 功能描述: |
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