参数资料
型号: CS6403-IL
厂商: CIRRUS LOGIC INC
元件分类: 编解码器
英文描述: Echo-Cancelling Codec
中文描述: A/MU-LAW, PCM CODEC, PQCC44
封装: PLASTIC, LCC-44
文件页数: 19/54页
文件大小: 761K
代理商: CS6403-IL
Register SSI_CR0
B11
RST
0
B10
SLP
0
B9
B8
B7
B6
B5
CE
0
B4
PED
0
B3
B2
B1
B0
AGCRD
0
NECD
0
FHPD
0
NHPD
0
GBC1
1
GBC0
0
AECB1 AECB0
1
0
This register is read from the SSI by the CPU only upon exit from Reset and Sleep. This register is
cleared at reset except for B3-B0 (see below).
BIT
NAME
VALUE
0
1
FUNCTION
RST
Reset
R
Normal operation.
Control registers and RAMs are cleared, and then
control constants are loaded into Data RAM. SSI is
still operational, though writes to any control bit
except RST are ignored.
Normal operation.
The CPU and AFP on the CS6403 are powered
down. Control registers and RAMs are unaffected.
Serial Data transactions that occur during power
down are transferred directly between the SSI and
the codec, bypassing the CPU. As a result, echo is
passed uncancelled.
SPKROUT volume is scaled to full-scale after
peak-limiter.
SPKROUT signal is peak-limited version of far-end
input.
10 ms of the available 64 ms of EC taps are
allocated by default to network echo cancellation.
No taps are allocated to network echo cancellation.
A high-pass filter ((1-D)/(1-0.75D)) is inserted in the
far-end input signal path.
This filter is bypassed.
A high-pass filter ((1-D)/(1-0.75D)) is inserted in the
near-end input signal path.
This filter is bypassed.
Data in 16-bit data modes is linear (i.e., not
companded).
b15 is still used as the steering bit, but if b15=0, the
least significant 8 bits are companded data.
A pre-emphasis filter is placed before the input to the
adaptive filter.
This filter is bypassed.
SLP
Sleep
0
1
R
AGCRD
AGC-Rescale Disable
0
R
1
NECD
NEC Disable
0
R
1
0
FHPD
FE_IN High-Pass
Disable
R
1
0
NHPD
NE_IN High-Pass Disable
R
1
0
CE
Companding Enable
R
1
PED
Pre-Emphasis Disable
0
R
1
"R" indicates value after Reset
CS6403
DS192PP6
19
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