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参数资料
| 型号： | CS6403-IL |
| 厂商： | CIRRUS LOGIC INC |
| 元件分类： | 编解码器 |
| 英文描述： | Echo-Cancelling Codec |
| 中文描述： | A/MU-LAW, PCM CODEC, PQCC44 |
| 封装： | PLASTIC, LCC-44 |
| 文件页数： | 41/54页 |
| 文件大小： | 761K |
| 代理商： | CS6403-IL |
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The far-end input gain is determined by R2, R3,
R9, and R10 which are all currently 10k
. The
resistors are part of a differential amplifier whose
gain is (-R2/R3). Note that R2 and R9 should
have the same value, as should R3 and R10.
Both FE_IN+ and FE_IN- are connected through
a 0.1
μ
F DC blocking capacitor.
The far-end output drive capability can be
boosted by using the PI, PO+ and PO- pins of
the MC145480. PI and PO- are equivalent to the
inverting input and output, respectively, of an
opamp. PO+ and PO- are differential drivers ca-
pable of driving a 150
load. Easy access to PI,
PO-, and PO+ is provided through J5, J6, and J7,
respectively. See the MC145480 datasheet and
Figure 5 for more details.
EPLD
The EMP7032 EPLD from Altera handles some
miscellaneous logic functions on the evaluation
board, but is not necessary for operation. It is
mainly used to encode the Algorithm Control
Switches (SW2-6) to the GPIN2/1/0 pins. It also
buffers the DIP switches, and it provides in-
verters for the LED bank.
The encoding of SW2-6 could have been done
without using programmable logic, but the
EPLD assures that only legal combinations of
buttons are accepted for all modes of operation
of the evaluation board. The EPLD provides the
function of several buffers, inverters, and
AND/OR gates. A Schmitt-trigger inverter U101
is added to provide hardware debouncing of the
switches.
An added benefit of the EPLD is that it demon-
strates effective use of separate ground planes for
analog and digital components. Although all of
the digital logic in the EPLD is relatively static,
the CDB6403 provides a good example of how
to split the digital and analog sides of a board.
Note that the CS6403 resides completely on the
analog side of the board and digital signals cross
the break in the ground planes by taking the
shortest possible route.
RO+
RO-
PI
PO-
PO+
VDD
FSR
DR
BCLKR
PDI
VAG
TI+
TI-
TG
MU/A
VSS
FST
DT
BCLKT
MCLK
AGND
R9
10k
20
C8
X7R
0.1
μ
F
R10
10k
0.1
μ
F
FE_IN-
18
R3
10k
C11
X7R
0.1
μ
F
FE_IN+
10k
R2
C9
X7R
19
17
UALAW
15
16
AGND
SYNCOUT
SDI
SCLK
14
13
11
12
1
3
2
4
6
5
7
8
10
9
X7R
0.1
μ
F
C5
FE_OUT+
FE_OUT-
+5VA
SDO
CONFIG
U3
MC145480
J5
Figure 5. On-board PCM Codec
CDB6403
DS192DB3
41
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PDF描述 |
|---|---|
| CS6403-IQ | Echo-Cancelling Codec |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| CS6403-IQ | 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:Echo-Cancelling Codec |
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